SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20130092926A1
• Filed: 10/01/2012
• Published: 04/18/2013
• Est. Priority Date: 10/13/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei
• Granted Patent: US 9,281,237 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A transistor which includes an oxide semiconductor and can operate at high speed is provided. A highly reliable semiconductor device including the transistor is provided. An oxide semiconductor layer including a pair of low-resistance regions and a channel formation region is provided over an electrode layer formed in a groove of a base insulating layer. The channel formation region is embedded in a position overlapping with a gate electrode which has a side surface provided with a sidewall. The groove includes a deep region and a shallow region. The sidewall overlaps with the shallow region, and a connection portion between a wiring and the electrode layer overlaps with the deep region.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

an insulating layer over the semiconductor substrate;

an oxide semiconductor film over the insulating layer;

a gate insulating layer over the oxide semiconductor film;

a gate electrode over the gate insulating layer, the gate electrode overlapping with the oxide semiconductor film;

a sidewall in contact with a side surface of the gate electrode;

a groove in the insulating layer, the groove comprising a deep region and a shallow region; and

a conductive region in the groove,

wherein the sidewall overlaps with the shallow region.

2. The semiconductor device according to claim 1, wherein a conductive layer is in contact with the sidewall and the oxide semiconductor film.

3. The semiconductor device according to claim 1, further comprising:

an interlayer insulating layer over the gate electrode; and

a wiring over the interlayer insulating layer,

wherein the wiring overlaps with the conductive region and is electrically connected to the deep region.

4. The semiconductor device according to claim 1, wherein the conductive region has a shallow region with a first width in a channel length direction and a deep region with a second width in the channel length direction.

5. The semiconductor device according to claim 1, wherein the oxide semiconductor film contains indium, gallium, and zinc.

6. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first insulating film over a first electrode layer;

performing first planarization treatment to expose a top surface of the first electrode layer;

forming a second electrode layer in contact with the top surface of the first electrode layer;

forming a second insulating film over the second electrode layer;

performing second planarization treatment to expose a top surface of the second electrode layer;

forming an oxide semiconductor film in contact with the top surface of the second electrode layer;

forming a gate insulating layer over the oxide semiconductor film;

forming a gate electrode over the gate insulating layer and an insulating film covering a top surface of the gate electrode;

forming a sidewall overlapping with the second electrode layer and in contact with a side surface of the gate electrode;

forming a conductive film over and in contact with the oxide semiconductor film, the conductive film covering the gate electrode and the sidewall; and

performing third planarization treatment to remove a part of the conductive film, which overlaps with the gate electrode.

7. The method for manufacturing a semiconductor device according to claim 6, wherein the oxide semiconductor film contains indium, gallium, and zinc.