FINFET DEVICE AND METHOD OF MANUFACTURING SAME

• US 20130092984A1
• Filed: 10/13/2011
• Published: 04/18/2013
• Est. Priority Date: 10/13/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liu, Chi-Wen, Wang, Chao-Hsiung
• Granted Patent: US 8,723,236 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7845 the means being a conductive material, e.g. silicided S/D or Gate
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure including one or more fins disposed on the substrate. The semiconductor device further includes a dielectric layer disposed on a central portion of the fin structure and traversing each of the one or more fins. The semiconductor device further includes a work function metal disposed on the dielectric layer and traversing each of the one or more fins. The semiconductor device further includes a strained material disposed on the work function metal and interposed between each of the one or more fins. The semiconductor device further includes a signal metal disposed on the work function metal and on the strained material and traversing each of the one or more fins.

Claims

1. A semiconductor device comprising:

a substrate including a fin structure disposed over the substrate, the fin structure including one or more fins;

an insulation material disposed on the substrate and formed in a region between each of the one or more fins;

a dielectric layer traversing each of the one or more fins and formed on the insulation material in the region between each of the one or more fins;

a work function metal traversing each of the one or more fins and formed on the dielectric layer in the region between each of the one or more fins;

a strained material disposed on the work function metal in the region between each of the one or more fins; and

a signal metal traversing each of the one or more fins and formed on the work function metal and on the strained material.

2. The semiconductor device of claim 1 wherein the strained material has a coefficient of thermal expansion (CTE) that is different than a CTE of the work function metal and a CTE of the signal metal, and

wherein the signal metal separates source and drain regions of the semiconductor device, the source and drain regions defining a channel region, for each of the one or more fins, therebetween.

3. The semiconductor device of claim 2 wherein the strained material induces a compressive stress in a current flow direction of the channel region, for each of the one or more fins.

4. The semiconductor device of claim 2 wherein the strained material induces a tensile stress in a current flow direction of the channel region, for each of the one or more fins.

5. The semiconductor device of claim 1 wherein the semiconductor device is one of a P-type metal-oxide-semiconductor (PMOS) fin-like field effect transistor (FinFET) device or a N-type metal-oxide-semiconductor (NMOS) FinFET device, and wherein the semiconductor device is included in an integrated circuit device.

6. The semiconductor device of claim 1 wherein the strained material is selected from the group consisting of a dielectric material and a metal material.

7. The semiconductor device of claim 1 wherein the strained material includes titanium silicide (TiSi) and the work function metal includes titanium nitride (TiN).

8. The semiconductor device of claim 1 wherein the strained material includes polyimide (PI) and the work function metal includes titanium aluminide (TiAl).

9. A semiconductor device comprising:

a substrate;

a fin structure including one or more fins disposed over the substrate;

a dielectric layer disposed on a central portion of the fin structure and traversing each of the one or more fins;

a work function metal disposed on the dielectric layer and traversing each of the one or more fins;

a strained material disposed on the work function metal and interposed between each of the one or more fins; and

a signal metal disposed on the work function metal and on the strained material and traversing each of the one or more fins.

10. The semiconductor device of claim 9 wherein the signal metal separates source and drain regions of the semiconductor device, the source and drain regions defining a channel region, for each of the one or more fins, therebetween,

wherein the strained material induces a compressive stress in a current flow direction of the channel region of at least one fin of the one or more fins of the fin structure, and

wherein the strained material has a coefficient of thermal expansion (CTE) that is less than a CTE of the work function metal and different than a CTE of the signal metal.

11. The semiconductor device of claim 9 wherein the signal metal separates source and drain regions of the semiconductor device, the source and drain regions defining a channel region, for each of the one or more fins, therebetween,

wherein the strained material induces a tensile stress in a current flow direction of the channel region of at least one fin of the one or more fins of the fin structure, and

wherein the strained material has a coefficient of thermal expansion (CTE) that is greater than a CTE of the work function metal and different than a CTE of the signal metal.

12. The semiconductor device of claim 10 wherein the semiconductor device is a P-type metal-oxide-semiconductor (PMOS) fin-like field effect transistor (FinFET) device.

13. The semiconductor device of claim 11 wherein the semiconductor device is a N-type metal-oxide-semiconductor (NMOS) fin-like field effect transistor (FinFET) device.

14. A method of manufacturing a semiconductor device, comprising:

providing a substrate;

forming a fin structure including one or more fins over the substrate, each of the one ore more fins including first and second sidewalls;

depositing an insulation material on the substrate and the fin structure, the insulation material substantially filling a region between each of the one or more fins;

removing a portion of the insulation material from the region between each of the one ore more fins such that a portion of the first and second sidewalls of each of the one or more fins is exposed;

forming a dielectric layer over a central portion of each of the one or more fins;

forming a work function metal over the dielectric layer and disposed in the region between each of the one or more fins;

forming a strained material on the work function metal, the strained material being disposed in the region between each of the one or more fins; and

etching back the strained material in the region between each of the one or more fins.

15. The method of claim 14 further comprising:

forming a signal metal over the work function metal and the etched back strained material, the signal metal traversing each of the one or more fins and separating source and drain regions of the semiconductor device, the source and drain regions defining a channel region, for each of the one or more fins, therebetween; and

forming source and drain features in the source and drain regions,

wherein forming the source and drain features includes recessing a portion of each of the one or more fins and epitaxially (epi) growing a semiconductor material on the recessed portions of each of the one or more fins.

16. The method of claim 14 wherein forming the strained material includes:

a spin-on process; and

a process temperature less than an operating temperature of the semiconductor device.

17. The method of claim 14 wherein forming the strained material includes:

a spin-on process; and

a process temperature greater than an operating temperature of the semiconductor device.

18. The method of claim 16 wherein forming the strained material includes depositing a metal material having a coefficient of thermal expansion (CTE) less than a CTE of the work function metal.

19. The method of claim 16 wherein forming the strained material includes depositing a dielectric material having a coefficient of thermal expansion (CTE) greater than a CTE of the work function metal.

20. The method of claim 17 wherein forming the strained material includes depositing a material having a coefficient of thermal expansion (CTE) less than a CTE of the work function metal and different than a CTE of the signal metal.