SELECTIVE FIN-SHAPING PROCESS USING PLASMA DOPING AND ETCHING FOR 3-DIMENSIONAL TRANSISTOR APPLICATIONS

• US 20130093026A1
• Filed: 10/14/2011
• Published: 04/18/2013
• Est. Priority Date: 10/14/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: WANN, Clement Hsingjen, LIN, Yi-Tang, CHANG, Chih-Sheng, SHIH, Chi-Yuan, LIU, Chi-Wen, YEH, Ling-Yen
• Granted Patent: US 8,946,829 B2
• Time in Patent Office: Days
• US Class Current: 257/401
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/06 characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/7854 with rounded corners

Abstract

A semiconductor apparatus includes fin field-effect transistor (FinFETs) having shaped fins and regular fins. Shaped fins have top portions that may be smaller, larger, thinner, or shorter than top portions of regular fins. The bottom portions of shaped fins and regular fins are the same. FinFETs may have only one or more shaped fins, one or more regular fins, or a mixture of shaped fins and regular fins. A semiconductor manufacturing process to shape one fin includes forming a photolithographic opening of one fin, optionally doping a portion of the fin, and etching a portion of the fin.

Claims

1. An apparatus comprising:

a semiconductor substrate; and

,

a plurality of fin field-effect transistors (FinFETs) on the substrate, said FinFETs having at least one fin;

wherein at least one of the plurality of FinFETs includes at least one shaped fin.

2. The apparatus of claim 1, wherein the at least one shaped fin is smaller than other fins of a same FinFET.

3. The apparatus of claim 2, wherein the at least one shaped fin is two or more fins not placed adjacent to each other.

4. The apparatus of claim 1, wherein the at least one shaped fin includes a portion that is thinner than other fins of a same FinFET.

5. The apparatus of claim 1, wherein the at least one shaped fin is larger than other fins of a same FinFET.

6. The apparatus of claim 1, wherein a portion of the at least one of the plurality of FinFETs is a single-fin FinFET.

7. The apparatus of claim 1, wherein a portion of the at least one of the plurality of FinFETs includes at least one shaped fin of a first shape and another portion of the plurality of FinFETs includes at least one shaped fin of a second shape and wherein the first shape and the second shape are different.

8. The apparatus of claim 1, wherein the at least one shaped fin has sloped sidewalls.

9. A fin field-effect transistor (FinFET) comprising:

a semiconductor substrate;

a plurality of fins on the substrate including one or more regular fins and one or more shaped fins, wherein regular fins and shaped fins have different top portion shapes; and

,

an oxide layer on the semiconductor substrate embedding a bottom portion of the plurality of fins

wherein the embedded bottom portion of the plurality of fins have substantially the same shape.

10. The transistor of claim 9, wherein the one or more shaped fins include at least one shaped fin of a first shape and at least one shaped fin of a second shape.

11. The transistor of claim 9, wherein the one or more shaped fins is smaller than the one or more regular fins.

12. The transistor of claim 9, wherein the one or more shaped fins is larger than the one or more regular fins.

13. The transistor of claim 9, wherein the one or more shaped fins are each adjacent to only the one or more regular fins such that the spacing between adjacent fins in the transistor is uniform.

14. The transistor of claim 9, wherein the plurality of fins and the semiconductor substrate are a same material.

15. A method of forming a fin field-effect transistor (FinFET), said method comprising:

forming a plurality of fins partially embedded in a shallow trench isolation (STI) layer on a semiconductor substrate;

patterning a photoresist layer over the plurality of fins to form one or more openings exposing a single fin; and

,

shaping the exposed single fin.

16. The method of claim 15, wherein shaping the exposed single fin comprises:

doping a portion of the exposed single fin with a dopant,

removing the doped portion of the exposed single fin.

17. The method of claim 15, wherein shaping the exposed single fin comprises:

etching a portion of the exposed single fin.

18. The method of claim 16, wherein the removing operation comprises etching.

19. A method of forming a fin field-effect transistor (FinFET), said method comprising:

forming a plurality of fins partially embedded in a shallow trench isolation (STI) layer on a semiconductor substrate;

depositing a dielectric layer over the STI layer to completely cover the plurality of fins;

patterning a photoresist layer over the dielectric layer to form one or more openings over a single fin;

etching through the dielectric layer to expose a single fin;

removing the photoresist layer; and

,

shaping the exposed single fin.

20. The method of claim 19, wherein shaping the exposed single fin comprises epitaxially growing fin material.