POST-PASSIVATION INTERCONNECT STRUCTURE

• US 20130093077A1
• Filed: 10/13/2011
• Published: 04/18/2013
• Est. Priority Date: 10/13/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: LIANG, Shih-Wei, CHEN, Hsien-Wei, CHEN, Ying-Ju, YU, Tsung-Yuan, LII, Mirng-Ji
• Granted Patent: US 8,581,400 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 21/76841 Barrier, adhesion or liner layers
• CPC Class Codes: H01L 2224/02235 Reinforcing structures
• CPC Class Codes: H01L 2224/02255 Shape of the auxiliary member
• CPC Class Codes: H01L 2224/0226 Material of the auxiliary member
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03452 Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/0346 Plating
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05609 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05664 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/11334 : using preformed bumps
• CPC Class Codes: H01L 2224/11849 : Reflowing
• CPC Class Codes: H01L 2224/13006 : Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13022 : the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13113 : Bismuth [Bi] as principal constituent
• CPC Class Codes: H01L 2224/13116 : Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81411 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/81413 : Bismuth [Bi] as principal constituent
• CPC Class Codes: H01L 2224/81416 : Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/81439 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/81447 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/81455 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3171 : the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/3192 : Multilayer coating
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides

Abstract

A semiconductor device includes a passivation layer, a first protective layer, an interconnect layer, and a second protective layer successively formed on a semiconductor substrate. The interconnect layer has an exposed portion, on which a barrier layer and a solder bump are formed. At least one of the passivation layer, the first protective layer, the interconnect layer and the second protective layer includes at least one slot formed in a region outside a conductive pad region.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate having a first region and a second region, wherein the first region is a conductive pad region, and the second region is adjacent to the first region;

a passivation layer overlying the semiconductor substrate;

a first protective layer overlying the passivation layer;

an interconnect layer overlying the first protective layer;

a second protective layer overlying the interconnect layer and comprising an opening exposing a portion of the interconnect layer;

a barrier layer formed on the exposed portion of the interconnect layer; and

a solder bump formed on the barrier layer,

wherein at least one of the passivation layer, the first protective layer, the interconnect layer, and the second protective layer comprises at least one slot formed in the second region.

2. The semiconductor device of claim 1, wherein the passivation layer comprises a plurality of slots in the second region, and the first protective layer fills the plurality of slots of the passivation layer.

3. The semiconductor device of claim 1, wherein the barrier layer comprises at least one of a nickel (Ni) layer, a palladium (Pd) layer, or a gold (Au) layer.

4. The semiconductor device of claim 1, wherein the interconnect layer comprises copper.

5. The semiconductor device of claim 1, further comprising a conductive pad formed on the semiconductor substrate in the first region, wherein the conductive pad is partially covered by the passivation layer and the first protective layer, and the conductive pad is electrically connected to the interconnect layer.

6. The semiconductor device of claim 1, wherein the first protective layer comprises a plurality of slots in the second region, and the interconnect layer fills the plurality of slots of the first protective layer.

7. The semiconductor device of claim 6, wherein the interconnect layer comprises a landing pad region exposed by the opening of the second protective layer, and a dummy region formed in the slots of the first protective layer and electrically separated from the landing pad region.

8. The semiconductor device of claim 1, wherein the first protective layer comprises a polymer.

9. The semiconductor device of claim 1, wherein the interconnect layer comprises a landing pad region exposed by the second protective layer and a dummy pad region electrically separated from the landing pad region, and the dummy pad region comprises a plurality of slots in the second region.

10. The semiconductor device of claim 9, wherein the second protective layer fills the plurality of slots in the dummy pad region of the interconnect layer.

11. The semiconductor device of claim 10, wherein the second protective layer comprises a plurality of slots exposing the dummy pad region of the interconnect layer.

12. The semiconductor device of claim 11, wherein the barrier layer fills the plurality of slots in the second protective layer.

13. The semiconductor device of claim 1, wherein the second protective layer comprises a polymer.

14. A packaging assembly, comprising:

a semiconductor device having a first region and a second region adjacent to the first region, and comprising;

a conductive pad formed on the first region;

a passivation layer formed on the first region and the second region, wherein the passivation layer comprises a first opening in the first region to partially cover the conductive pad;

a first polymer layer overlying the passivation layer and comprising a second opening in the first region to partially cover the first opening and partially expose the conductive pad;

a post-passivation interconnect (PPI) structure overlying the first polymer layer and filling the second opening of the first polymer layer;

a second polymer layer overlying the PPI structure and comprising a third opening exposing a landing pad region of the PPI structure; and

a barrier layer on the exposed landing pad region of the PPI structure, wherein the barrier layer comprises at least one of a nickel (Ni) layer, a palladium (Pd) layer or a gold (Au) layer;

a substrate comprising a conductive region; and

a joint solder structure between the barrier layer of the semiconductor device and the conductive region of the substrate,

wherein at least one of the passivation layer, the first polymer layer, the PPI structure, and the second polymer layer comprises at least one slot formed in the second region.

15. The packaging assembly of claim 14, wherein the passivation layer comprises a plurality of slots in the second region, and the first polymer layer fills the plurality of slots of the passivation layer.

16. The packaging assembly of claim 14, wherein the first polymer layer comprises a plurality of slots in the second region, and the PPI structure fills the plurality of slots of the first polymer layer to form a dummy region which is electrically separated from the landing pad region.

17. The packaging assembly of claim 14, wherein the PPI structure comprises a dummy pad region electrically separated from the landing pad region, and the dummy pad region comprises a plurality of slots in the second region.

18. The packaging assembly of claim 17, wherein the second polymer layer fills the plurality of slots in the dummy pad region of the PPI structure.

19. The packaging assembly of claim 18, wherein the second polymer layer comprises a plurality of slots exposing the dummy pad region of the PPI layer.

20. The packaging assembly of claim 19, wherein the barrier layer fills the plurality of slots in the second polymer layer.