SEMICONDUCTOR DEVICE

• US 20130093096A1
• Filed: 12/07/2012
• Published: 04/18/2013
• Est. Priority Date: 10/09/2009
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: FURUMIYA, Masayuki, NAKASHIBA, Yasutaka, TANABE, Akira
• Granted Patent: US 8,604,617 B2
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 2223/6627 Waveguides, e.g. microstrip line, strip line, coplanar line
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/1903 including wave guides
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A semiconductor device with a transistor region has a first conductor pattern formed within a multilayer interconnect structure positioned under a signal line and above the transistor region. The first conductor pattern is coupled to ground or a power supply and overlaps the transistor region. The signal line overlaps the first conductor pattern.

Claims

1. A semiconductor device comprising:

a transistor formed in a transistor region on a substrate;

a multilayer interconnect structure formed over the transistor region;

a first conductor pattern formed in the multilayer interconnect structure to overlap the transistor region, said first conductor pattern being coupled to ground or to a power supply;

a first dielectric layer formed over the multilayer interconnect structure;

a signal line formed over the first dielectric layer in a region in which it overlaps the first conductor pattern in plan view, the signal line being part of a transmission line; and

two second conductor patterns formed in the same conductor layer as the signal line and, in a plan view, extending parallel to the signal line with the signal line between them,

wherein the second conductor patterns are electrically coupled to the first conductor pattern,

wherein a distance from the signal line to the second conductor patterns is greater than a height form the first conductor pattern to the signal line.

2. The semiconductor device according to claim 1, wherein the first dielectric layer is comprised of an organic layer.

3. The semiconductor device according to claim 2, further comprising:

a second dielectric layer formed on the signal line and the two second conductor patterns such that the second dielectric layer is arranged between the signal line and the second conductor patterns,

wherein the second dielectric layer is comprised of an organic layer.

4. The semiconductor device according to claim 1, wherein the first conductor pattern is formed in the uppermost interconnect layer in the multilayer interconnect structure.

5. The semiconductor device according to claim 1, wherein the two second conductor patterns are formed over the first dielectric layer in a region in which it overlaps the first conductor pattern in plan view.

6. The semiconductor device according to claim 1, wherein a width of the second conductor patterns is larger than a width of the signal line.

7. The semiconductor device according to claim 1, wherein the signal line overlaps the transistor region.

8. The semiconductor device according to claim 7, further comprising another transistor region overlapping the first conductor pattern.

9. The semiconductor device according to claim 1, wherein the transistor is electrically connected to the signal line.

10. The semiconductor device according to claim 9, wherein the transistor is included in a RF amplifier.

11. The semiconductor device according to claim 10, further comprising an another transistor in an another transistor region overlapping the first conductor pattern,

wherein the another transistor is not coupled to the first conductor pattern.

12. The semiconductor device according to claim 10, further comprising an another transistor in an another transistor region overlapping the first conductor pattern,

wherein the another transistor is included in an another amplifier using a different frequency from the RF amplifier.