SEMICONDUCTOR DEVICE AND STRUCTURE

• US 20130095580A1
• Filed: 10/18/2011
• Published: 04/18/2013
• Est. Priority Date: 10/18/2011
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Sekar, Deepak C., Cronquist, Brian, Wurman, Ze'ev
• Granted Patent: US 9,029,173 B2
• Time in Patent Office: Days
• US Class Current: 438/17
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/0694 : comprising components formed on opposite sides of a semiconductor substrate
• CPC Class Codes: H01L 27/088 : the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 : complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/11803 : using field effect technology
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/7841 : with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H10B 10/125 : the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 10/18 : Peripheral circuit regions
• CPC Class Codes: H10B 12/09 : with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/35 : with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/35 : with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 63/30 : comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/80 : Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10B 63/845 : the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/023 : by chemical vapor deposition, e.g. MOCVD, ALD
• CPC Class Codes: H10N 70/066 : by filling of openings, e.g. damascene method
• CPC Class Codes: H10N 70/20 : Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/823 : adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx

Abstract

A method for formation of a semiconductor device including a first mono-crystalline layer comprising first transistors and first alignment marks, the method comprising forming a doped layer within a wafer, forming a second mono-crystalline layer on top of the first mono-crystalline layer by transferring at least a portion of the doped layer using layer transfer step, and processing second transistors on the second mono-crystalline layer comprising a step of forming a gate dielectric, wherein the second transistors are horizontally oriented.

Claims

1. A method for formation of a semiconductor device, the method comprising:

providing a first mono-crystalline layer comprising first transistors and first alignment marks;

forming a doped layer within a wafer;

forming a second mono-crystalline layer on top of said first mono-crystalline layer by transferring at least a portion of said doped layer using layer transfer step, and

processing second transistors on said second mono-crystalline layer comprising a step of forming a gate dielectric,

wherein said second transistors are horizontally oriented.

2. A method according to claim 1, comprising providing at least one metal layer overlying said first mono-crystalline silicon layer, wherein said at least one metal layer comprises copper or aluminum;

and provides interconnection for said first transistors.

3. A method according to claim 1, comprising forming a low power mobile system by integrating in said semiconductor device.

4. A method according to claim 1, comprising performing a lithography step followed by a processing step affecting the formation of said first transistors and also said second transistors.

5. A method according to claim 1, comprising:

replacing a signal generated by said first transistors by a signal generated by said second transistor, or replacing a signal generated by said second transistors by a signal generated by said first transistors.

6. A method according to claim 1, wherein at least one of said second transistors is one of:

(i) a recessed-channel transistor (RCAT);

(ii) a junction-less transistor;

(iii) a replacement-gate transistor;

(iv) a trench MOSFET transistor;

(v) a double gate transistor;

(vi) a Finfet type transistor;

or

(vii) a Dopant Segregated Schottky (DSS-Schottky) transistor.

7. A method according to claim 1, comprising a step of annealing after said layer transfer step.

8. A method according to claim 1, wherein at least one of said second transistors is a p-type transistor and at least one of said second transistors is an n-type transistor.

9. A method according to claim 1, wherein said wafer comprises second alignment mark, and comprising a lithography step wherein the alignment is based on said first alignment mark and said second alignment mark.

10. A method according to claim 1, comprising a follow on step of etching some of said second transistors.

11. A method according to claim 1, wherein said layer transfer comprises a prior etch step for the formation of an etch stop indicator.

12. A method according to claim 1, comprising a step of partitioning a logic design to a first portion to be constructed using said first transistors and second portion to be constructed by said second transistors wherein said step of partitioning is done so the lithography tool required for the construction of said second portion costs at least 20% less than the lithography tool required for the construction of said first portion.

13. A method according to claim 1, comprising implementing logic design on said device, wherein said step of implementing comprises a synthesis step utilizing at least two libraries, wherein one of said libraries utilized more aggressive design rules than the other.

14. A method according to claim 1, comprises memory array comprising said second transistors, wherein said memory array is a floating body DRAM array.

15. A method according to claim 1, wherein said layer transfer step comprise carrier wafer.

16. A method according to claim 1, wherein

said first transistor forms at least one first logic circuit;

and

said second transistor form at least one second logic circuit, wherein

said second logic circuit overlay said first logic circuit, and

performing a step of testing said device and a follow on step of replacing;

said first logic circuit by said second logic circuit, or

said second logic circuit by said first logic circuit.

17. A method for formation of a semiconductor device, the method comprising:

providing a first wafer comprising a first single crystal layer comprising first transistors;

implanting to form a doped layer within a second wafer;

forming a second mono-crystalline layer on top of said first wafer by transferring at least a portion of said doped layer using layer transfer step, and

completing the formation of second transistors on said second mono-crystalline layer, wherein

said first transistor forms at least one first logic circuit; and

said second transistor form at least one second logic circuit, wherein

said second logic circuit overlay said first logic circuit, and

performing a step of testing said device and a follow on step of replacing;

said first logic circuit by said second logic circuit, or

said second logic circuit by said first logic circuit.

18. A method according to claim 17, further comprising:

replacing a signal generated by said first transistors by a signal generated by said second transistor, or replacing a signal generated by said second transistors by a signal generated by said first transistors.

19. A method according to claim 17, comprising a step of comparing a signal generated by said at least one first logic circuit to a signal generated by said at least one second logic circuit.

20. A method according to claim 17, comprising a step of removing a power supply from either said at least one first logic circuit or said at least one second logic circuit.

21. A method for formation of a semiconductor device, the method comprising:

providing a first wafer comprising a first single crystal layer comprising first transistors;

implanting to form a doped layer within a second wafer;

forming a second mono-crystalline layer on top of said first wafer by transferring at least a portion of said doped layer using layer transfer step, and

completing the formation of second transistors on said second mono-crystalline layer, and processing connection layers on top of said second mono-crystalline layer, wherein

said connection layers comprise at least one connection path that is designed to conduct heat and not to conduct electricity.

22. A method according to claim 21, comprising a step of depositing at least one electrical isolation region between at least two of said second transistors, wherein said electrical isolation region is designed to conduct heat.

23. A method according to claim 21, comprising a step of depositing a heat spreader layer between said second mono-crystalline layer and said first single crystal layer.

24. A method according to claim 21, wherein said connection path is between the power bus and an isolation layer between two of said second transistors.

25. A method according to claim 21, comprising designing the power busses of said semiconductor device based on heat removal criteria.

26. A method for formation of a semiconductor device, the method comprising:

providing a first wafer comprising first mono-crystalline layer comprising first transistors, and

comprising a step of implant to form second transistors within a second mono-crystalline layer, and

transferring a second mono-crystalline layer on top of said first mono-crystalline layer wherein

said method comprises the use of at least ten masks, each with its own unique patterns, and

wherein said method is used for formation of at least two devices which are substantially different by the amount of logic, memory or input-output cells they have, wherein each of said two devices has been formed using the same said at least ten masks.

27. A method according to claim 26, comprising the step of formation of dice lines by etching pre-patterned layers.

28. A method according to claim 26, wherein at least one of said two devices comprises unused potential dice lines.

29. A method according to claim 26, wherein the formation of at least one of said two devices comprises the step of using custom mask to form connection over unused potential dice lines, and wherein the formation of the other of said two devices does not use said custom mask.

30. A method according to claim 26, wherein said second mono-crystalline layer comprises connection layers interconnecting said second transistors, and wherein

said transferring comprises the use of through silicon vias (TSVs) to connect said second transistors to said first transistors.