Device and Method for Manufacturing a Device

• US 20130095609A1
• Filed: 12/07/2012
• Published: 04/18/2013
• Est. Priority Date: 04/01/2010
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Theuss, Horst
• Granted Patent: US 8,669,143 B2
• Time in Patent Office: Days
• US Class Current: 438/107
• CPC Class Codes: B81C 1/0023 Packaging together an electronic processing unit die and a micromechanical structure die MEMS packages B81B7/0032; MEMS packaging processes B81C1/00261
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: G01P 1/023 for acceleration measuring devices
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/1306 Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13062 Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A device includes a first semiconductor chip and a first encapsulant that encapsulates the first semiconductor chip and that includes a cavity. A carrier and an electrical component are mounted on the carrier. The carrier is arranged such that the electrical component is enclosed by the cavity.

Claims

1. A method for manufacturing a device, the method comprising:

encapsulating a first semiconductor chip with a first encapsulant, wherein the first encapsulant comprises a cavity;

mounting an electrical component on a carrier; and

placing the carrier on a first main surface of the encapsulant such that the electrical component is enclosed by the cavity.

2. The method of claim 1, wherein encapsulating the first semiconductor chip with a first encapsulant comprises encapsulating the first semiconductor chip with a molding compound and forming the cavity in a molding tool.

3. The method of claim 1, further comprising forming an electrical through connection through the first encapsulant.

4. The method of claim 3, further comprising forming a first redistribution layer on a second main surface of the encapsulant, the second main surface connecting the through connection.

5. The method of claim 4, further comprising forming a second redistribution layer on the first main surface of the encapsulant, the second redistribution layer connecting the through connection.

6. The method of claim 1, further comprising mounting the first semiconductor chip on a support carrier before encapsulating the first semiconductor chip and removing the support carrier after encapsulating the first semiconductor chip.

7. The method of claim 1, further comprising forming an aperture in the first encapsulant.

8. The method of claim 1, further comprising encapsulating a second semiconductor chip with a second encapsulant.

9. The method of claim 1, wherein the electrical component is a MEMS device.

10. The method of claim 1, wherein the electrical component is a power supply.

11. A method for manufacturing a packaged semiconductor device, the method comprising:

encapsulating semiconductor chips such that a cavity is formed on a first main surface of an encapsulant and over each semiconductor chips;

forming a redistribution layer over a second main surface of the encapsulant such that the semiconductor chips are connected to the redistribution layer;

forming first through vias in the encapsulant such that the first main surface is connected to the second main surface;

locating a semiconductor components in the cavities by placing an assembled semiconductor component on the first main surface of the encapsulant; and

singulating the encapsulant forming the packaged semiconductor device such that the packaged semiconductor device comprises a first semiconductor chip, a second semiconductor chip, a first through via and a semiconductor component.

12. The method of claim 11, wherein the assembled semiconductor component is formed comprising:

encapsulating a second semiconductor chip in a second encapsulant;

forming a second redistribution layer on a first main surface of the second encapsulant; and

mounting the semiconductor component on the second redistribution layer.

13. The method of claim 12, further comprising connecting the semiconductor component to the first through via through a first bond wire and the second redistribution layer.

14. The method of claim 11, further comprising connecting the semiconductor component to the first through via along the first main surface of the first main surface of the encapsulant.

15. The method of claim 11, further comprising forming second through vias in the encapsulant such that the first main surface is connected to the second main surface and singulating the encapsulant such that the packaged semiconductor device further comprises a second through via.

16. A method for manufacturing a device, the method comprising:

encapsulating a first semiconductor chip with a first encapsulant;

forming a first redistribution layer on the first encapsulant;

placing an electrical component on the first redistribution layer;

forming a second encapsulant having a cavity; and

placing a first main surface of the second encapsulant on a first main surface of the first encapsulant such that the electrical component is enclosed by the cavity.

17. The method of claim 16, further comprising forming an aperture in the second encapsulant.

18. The method of claim 16, further comprising encapsulating a semiconductor chip with the second encapsulant, forming a first through via connecting the first main surface of the second encapsulant and a second main surface of the second encapsulant, and forming a second redistribution layer on the second main surface of the second encapsulant.

19. The method of claim 18, further comprising forming a second through via in the second encapsulant, the second through via connecting the second main surface of the encapsulant with the first mains surface of the encapsulant.

20. The method of claim 18, further comprising forming a ball grid array or a land grid array on the second redistribution layer.