METHODS OF MANUFACTURING A VERTICAL TYPE SEMICONDUCTOR DEVICE

• US 20130095654A1
• Filed: 08/30/2012
• Published: 04/18/2013
• Est. Priority Date: 10/14/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Dae-Hyun Jang, Kyoung-Sub Shin, Seong-Soo Lee, Yong-Hyun Kwon
• Inventors: JANG, Dae-Hyun, LEE, Seong-Soo, SHIN, Kyoung-Sub, KWON, Yong-Hyun
• Granted Patent: US 8,871,591 B2
• Time in Patent Office: Days
• US Class Current: 438/666
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

According to example embodiments of inventive concepts, a method includes forming cell patterns and insulating interlayers between the cell patterns on the substrate. An upper insulating interlayer including initial and preliminary contact holes is formed on an uppermost cell pattern. A first reflection limiting layer pattern and a first photoresist layer pattern are formed for exposing a first preliminary contact hole while covering inlet portion of the initial and preliminary contact holes. A first etching process is performed on layers under the first preliminary contact hole to expose the cell pattern at a lower position than a bottom of the first preliminary contact hole. A partial removing process of sidewall portions of the first reflection limiting layer pattern and the first photoresist layer pattern and an etching process on exposed layers through bottom portions of the preliminary contact holes are repeated for forming contact holes having different depths.

Claims

1. A method of manufacturing a semiconductor device comprising:

forming cell patterns and insulating interlayers between each of the cell patterns on a substrate,

the cell patterns surrounding vertically extruded semiconductor patterns;

forming an upper insulating interlayer on an uppermost cell pattern of the cell patterns,

the upper insulating layer defining initial and preliminary contact holes;

forming a first reflection limiting layer pattern and a first photoresist layer pattern on the upper insulating interlayer,

the first photoresist layer pattern and the first reflection limiting layer pattern exposing a first preliminary contact hole of the preliminary contact holes at a first position from an edge portion of the upper insulating layer,

the first photoresist layer pattern and the first reflection limiting layer pattern covering an inlet portion of the initial and preliminary contact holes;

performing a first etching process with respect to layers under the first preliminary contact hole to expose a cell pattern at a lower position than a bottom of the first preliminary contact hole;

repeating a partial removing process of sidewall portions of the first reflection limiting layer pattern and the first photoresist layer pattern and an etching process with respect to exposed layers through bottom portions of the preliminary contact holes one by one, for forming contact holes having decreasing depths from the edge portion to a center portion of the cell patterns;

forming an insulating spacer on sidewalls of the contact holes; and

filling up inner portions of the contact holes including the insulating spacer with a conductive material to form contacts.

2. The method of manufacturing a semiconductor device of claim 1, wherein at least one of the contacts is at an exterior side portion of one of the semiconductor patterns.

3. The method of manufacturing a semiconductor device of claim 1, wherein the forming contact holes includes:

partially removing the sidewall portions of the first photoresist pattern and the first reflection limiting layer pattern to form a second refection limiting layer pattern and a second photoresist pattern for selectively exposing first and second preliminary contact holes of the preliminary contact holes, respectively, at first and second positions from the edge portion of the upper insulating layer;

performing a second etching with respect to layers exposed through the first and second preliminary contact holes to expose an upper surface of the cell pattern provided at a lower position than respective bottom portions of the first and second preliminary contact holes; and

repeating a partial removing process of the sidewall portions of the reflection limiting layer pattern and the photoresist layer pattern and an etching process with respect to exposed layers through bottom portions of the preliminary contact holes one by one, until a lowermost cell pattern of the cell patterns is exposed through the first preliminary contact hole at the first edge portion of the upper insulating layer.

4. The method of manufacturing a semiconductor device of claim 1, further comprising:

forming a hard mask pattern on the upper insulating interlayer.

5. The method of manufacturing a semiconductor device of claim 1, wherein

the cell patterns include contact forming layers, and

the contacts formed by the conductive material connect to the contact forming layers.

6. The method of manufacturing a semiconductor device of claim 5, wherein the contact forming layers include a conductive substance for forming wirings.

7. The method of manufacturing a semiconductor device of claim 5, wherein

the contact forming layers are sacrificial layers for forming conductive substance layers for wirings, and

the contact forming layers include an insulating material that has an etching selectivity with respect to the insulating interlayers.

8. The method of manufacturing a semiconductor device of claim 7, further comprising:

selectively removing the contact forming layers; and

filling up a metal into a space formed after the removal of the contact forming layers.

9. The method of manufacturing a semiconductor device of claim 5, wherein side end portions of the contact forming layers are in parallel.

10. The method of manufacturing a semiconductor device of claim 1, wherein one layer of the cell patterns and one layer of the insulating interlayers are etched while performing an etching process with respect to layers exposed through the preliminary contact holes.

11. The method of manufacturing a semiconductor device of claim 1, wherein the forming of the first reflection limiting layer pattern and the first photoresist layer pattern includes:

forming a reflection limiting layer covering the inlet portion of the initial and preliminary contact holes while keeping space in the initial and preliminary contact holes,

the reflection limiting layer being formed on the upper insulating interlayer;

forming a photoresist layer on the reflection limiting layer;

performing a photolithography process with respect to the photoresist layer to form the first photoresist layer pattern; and

etching the reflection limiting layer using the first photoresist layer pattern as a mask.

12. A method of forming an integrated wiring comprising:

alternately integrating first to n-th insulating interlayers and first to n-th contact forming layers on a substrate;

forming an upper insulating interlayer on an n-th contact forming layer of the first to n-th contact forming layers;

partially etching the upper insulating interlayer to form an upper insulating interlayer pattern that defines initial and preliminary contact holes;

forming a first reflection limiting layer pattern and a first photoresist pattern on the upper insulating layer for covering inlet portions of the initial and preliminary contact holes while selectively exposing first preliminary contact holes at first positions from edge portions of the upper insulating interlayer pattern;

performing a first etching of one of the first to n-th insulating interlayers and first to n-th contact forming layers exposed through the first preliminary contact holes to expose a contact forming layer at a lower position than a bottom portion of the first preliminary contact hole;

partially removing sidewalls of the first photoresist pattern and the first reflection limiting layer pattern to form a second reflection limiting layer pattern and a second photoresist pattern,

the second photoresist and reflection limiting patterns exposing first and second preliminary contact holes at first and second positions from the edge portions of the upper insulating interlayer pattern;

performing a second etching with respect to layers exposed through the first and second preliminary contact holes to expose the contact forming layers respectively provided at a lower position than the bottom portion of the first and second preliminary contact holes,

the contact holes having depths decreasing from the edge portion to a center portion of the;

forming an insulating spacer on the sidewalls of the contact holes; and

filling up a conductive material in the contact holes including the insulating spacer to form contacts.

13. The method of forming an integrated wiring of claim 12, wherein side end portions of the first to n-th contact forming layers are in parallel.

14. The method of forming an integrated wiring of claim 12, wherein the contact forming layers are word lines of a vertical type nonvolatile memory device.

15. The method of forming an integrated wiring of claim 12, wherein

the initial and preliminary contact holes are at a first region of the substrate,

the initial and preliminary contact holes expose an upper surface of the n-th contact forming layer, and

the initial and preliminary contact holes are at a second region of the substrate and make contact with the contact forming layer at a lower position than a position of the n-th contact forming layer.

16. A method of manufacturing a semiconductor device comprising:

forming 1 to n-th first and second layer patterns alternatingly stacked,

n being an integer greater than or equal to 3;

forming a mask pattern on the n-th second layer pattern of the 1 to n-th second layer patterns,

the mask pattern defining 1 to n-th openings spaced apart in a horizontal direction over a first portion of the n-th second layer pattern;

forming a first multilayer pattern on the mask pattern,

the first multilayer pattern including a first resist pattern on a first reflection limiting pattern,

the first multilayer pattern exposing one of the 1 to n-th openings of the mask pattern;

forming 1 to n-th contact holes having different depths through the 1 to n-th openings by,

(A) etching at least one of the 1 to n-th first and second layer patterns using the mask pattern and the first multilayer pattern as an etch mask and at least one of the 1 to (n−

1)-th second layer patterns as an etch stop,

(B) laterally removing part of the first multilayer pattern to expose another opening of the 1 to n-th openings of the mask pattern,

(C) repeating (A) and (B) until 1 to (n−

1)-th contact holes are formed, and

(D) removing a remaining portion of the first multilayer pattern to expose the n-th opening as the n-th contact hole; and

forming contacts by filling the 1 to n-th contact holes with a conductive material.

17. The method of claim 16, wherein

a material of at least one of the 1 to n-th first layer patterns is different than a material of at least one of the 1 to n-th second layer patterns.

18. The method of claim 16, wherein

a material of the mask pattern has an etching selectivity with respect to a material of the 1 to n-th first layer patterns and a material of the 1 to n-th second layer patterns.

19. The method of claim 16, further comprising:

a plurality of semiconducting patterns extending vertically through a central portion of the 1 to n-th first and second layer patterns,

wherein the central portion of the 1 to n-th first and second layer patterns is adjacent to the first portion of the of n-th second layer pattern.

20. The method of claim 16, wherein

the mask pattern on the n-th second layer pattern further defines 1 to k-th holes spaced apart in the horizontal direction over a second portion of the n-th second layer pattern;

k is an integer equal to n;

the first multilayer pattern exposes one hole of the 1 to k-th holes of the mask pattern; and

the forming 1 to n-th contact holes having different depths through the 1 to n-th openings further includes forming 1 to k-th contact trenches having different depths through the 1 to k-th holes of the mask pattern by,

exposing another hole of the 1 to k-th holes of the mask pattern during the (B) laterally removing part of the first multilayer pattern to expose another opening of the 1 to n-th openings of the mask pattern,

repeating the (A) and (B) until 1 to (k−

1)-th contact trenches are formed in addition to the 1 to (n−

1)-th contact holes,

exposing the k-th hole as the k-th contact trench during the (D) removing the remaining portion of the first multilayer pattern; and

the forming the contacts further includes filling the 1 to k-th contact trenches with the conductive material.