System and Method for High-Performance, Low-Power Data Center Interconnect Fabric

• US 20130097448A1
• Filed: 12/05/2012
• Published: 04/18/2013
• Est. Priority Date: 10/30/2009
• Status: Active Grant

• Current Assignee: Calxeda Inc.
• Original Assignee: Calxeda Inc.
• Inventors: Davis, Mark Bradley, Borland, David James
• Granted Patent: US 8,737,410 B2
• Time in Patent Office: Days
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 12/0284 Multiple user address space allocation, e.g. using different base addresses interprocessor communication G06F15/163
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 13/40 Bus structure for computer networks G06F15/163; for optical bus networks H04B10/25
• CPC Class Codes: G06F 3/0605 by facilitating the interaction with a user or administrator
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 9/5016 the resource being the memory
• CPC Class Codes: H04L 45/00 Routing or path finding of packets in data switching networks routing or path finding in wireless networks H04W40/00
• CPC Class Codes: H04L 45/60 Router architectures
• CPC Class Codes: H04L 45/74 Address processing for routing
• CPC Class Codes: H04L 45/74591 using content-addressable memories [CAM]
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 49/109 Integrated on microchip, e.g. switch-on-chip
• CPC Class Codes: H04L 49/15 Interconnection of switching modules
• CPC Class Codes: H04L 49/201 Multicast operation; Broadcast operation
• CPC Class Codes: H04L 49/25 Routing or path finding in a switch fabric
• CPC Class Codes: H04L 49/253 using establishment or release of connections between ports
• CPC Class Codes: H04L 49/3009 Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/351 : for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/356 : for storage area networks
• CPC Class Codes: Y02B 70/10 : Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
• CPC Class Codes: Y02B 70/30 : Systems integrating technologies related to power network operation and communication or information technologies for improving the carbon footprint of the management of residential or tertiary loads, i.e. smart grids as climate change mitigation technology in the buildings sector, including also the last stages of power distribution and the control, monitoring or operating management systems at local level
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/00 : Reducing energy consumption in communication networks

Abstract

A system and method are provided that support a routing using a tree-like or graph topology that supports multiple links per node, where each link is designated as an Up, Down, or Lateral link, or both, within the topology. The system may use a segmented MAC architecture which may have a method of re-purposing MAC IP addresses for inside MACs and outside MACs, and leveraging what would normally be the physical signaling for the MAC to feed into the switch.

Claims

1. A system on a chip, comprising:

one or more processing cores;

a switching fabric; and

one or more management processors coupled to the fabric switch and to each one of the one or more processing cores, wherein the management processor causes a communication request directed to a first one of the one or more processing cores to be held in the switching fabric while the first one of the one or more processing cores is in an inactive state and causes the communication request to be received by the first one of the one or more processing cores in response to the first one of the one or more processing cores being transitioned from the inactive state to an active state.

2. The system on a chip of claim 1 wherein:

the inactive state is a state in which electrical power allocated to the first one of the one or more processing cores is inadequate for performing a task requested in the communication request; and

the active state is a state in which electrical power allocated to the first one of the one or more processing cores is adequate for performing a task requested in the communication request

3. The system on a chip of claim 2 wherein the first processor is asleep when in the inactive state.

4. A system on a chip, comprising:

one or more processing cores;

a switching fabric; and

one or more management processors coupled to the fabric switch and to each one of the one or more processing cores, wherein the management processor causes a communication request directed to a first one of the one or more processing cores to be held in the switching fabric when the one or more management processors determine that the first one of the one or more processing cores is in an inactive state, wherein the one or more management processors assess the one or more processing cores to determine a second one of the one or more processing cores that is currently in a state allowing the second one of the one or more processing cores to perform the task initiated by the communication request, and wherein the one or more management processors cause the communication request to be delivered to the second one of the one or more processing cores for allowing the second one of the one or more processing cores to perform the task initiated by the communication request after determining that the second one of the one or more processing cores is currently in the state allowing the second one of the one or more processing cores to perform the task initiated by the communication request while the first one of the one or more processing cores remains in the inactive state.

5. The system on a chip of claim 4 wherein the second one of the one or more processing cores being in a state allowing the second one of the one or more processing cores to perform the task initiated by the communication request includes second one of the one or more processing cores having sufficient processing power available for performing the task to be initiated by the communication request.

6. The system on a chip of claim 5 wherein the first processor is asleep when in the inactive state.

7. A system on a chip, comprising:

one or more processing cores;

a switching fabric coupled to each one of the processor cores; and

one or more management processors coupled to the fabric switch and to each one of the one or more processing cores, wherein the one or more management processors enable each one of the one or more processing cores to be selectively transitioned between an inactive state and an active state, wherein the one or more management processors receive and respond to communication requests for a first one of the one or more processing cores while the first one of the one or more processing cores is in the inactive state, and wherein the one or more management processors enable the switching fabric to provide data associated with the communication request to the first one of the one or more processing cores after transitioning the first one of the one or more processing cores from the inactive state to the active state.

8. The system on a chip of claim 7 wherein:

the inactive state is a state in which electrical power allocated to the first one of the one or more processing cores is inadequate for performing a task requested in the communication request; and

the active state is a state in which electrical power allocated to the first one of the one or more processing cores is adequate for performing a task requested in the communication request.

9. The system on a chip of claim 8 wherein the first processor is asleep when in the inactive state.

10. A system on a chip node in a processing system, comprising:

one or more processing cores each capable of being operated at one or more different power levels;

one or more external communication interfaces allowing communication of information with one or more other systems;

a switching fabric coupled to each one of the processor cores, wherein the fabric switch allows selective communication between each one of the one or more processing cores and each one of the external communication interfaces;

one or more controllable power supply units each coupled to each one of the one or more processing cores for providing electrical power thereto;

one or more power management portions coupled between each one of the one or more processing cores and each one of the controllable power supply units, wherein the one or more power management portions determine a need for computation at each one of the one or more processing cores and wherein the one or more power management portions determine a manner in which to allocate electrical power from the controllable power supply units to each one of the one or more processing cores to meet the need for computation of each one of the one or more processing cores.

11. The system on a chip node of claim 10 wherein the one or more power management portions activate a particular one of the one or more controllable power supply units not currently supplying power to the one or more processing cores in order to allocate electrical power from the controllable power supply units to each one of the one or more processing cores to meet the need for computation of each one of the one or more processing cores.

12. The system on a chip node of claim 10 wherein:

each one of the one or more processing cores is allocated a base capacity of electrical power; and

the one or more power management portions negotiate with each one of the one or more processing cores in order to determine the manner in which to allocate electrical power from the controllable power supply units to each one of the one or more processing cores to meet the need for computation of each one of the one or more processing cores.

13. The system on a chip node of claim 12 wherein the one or more power management portions activate a particular one of the one or more controllable power supply units not currently supplying power to the one or more processing cores in order to allocate electrical power from the controllable power supply units to each one of the one or more processing cores to meet the need for computation of each one of the one or more processing cores.

14. The system on a chip node of claim 10 wherein the one or more power management portions cause a communication request directed to a first one of the one or more processing cores to be held in the switching fabric while the first one of the one or more processing cores is in an inactive state and causes the communication request to be received by the first one of the one or more processing cores in response to the first one of the one or more processing cores being transitioned from the inactive state to an active state.

15. The system on a chip node of claim 10 wherein:

the one or more power management portions enable each one of the one or more processing cores to be selectively transitioned between an active state and an inactive state;

the one or more power management portions receive and respond to communication requests for a first one of the one or more processing cores while the first one of the one or more processing cores is in the inactive state; and

the one or more power management portions enable the switching fabric to provide data associated with the communication request to the first one of the one or more processing cores after transitioning the first one of the one or more processing cores from the inactive state to the active state.

16. The system on a chip node of claim 10 wherein:

the one or more power management portions cause a communication request directed to a first one of the one or more processing cores to be held in the switching fabric when the one or more power management portions determine that the first one of the one or more processing cores is in an inactive state;

the one or more power management portions assess the one or more processing cores to determine a second one of the one or more processing cores that is currently in an active state; and

the one or more power management portions cause the communication request to be delivered to the second one of the one or more processing cores for allowing the second one of the one or more processing cores to perform the task initiated by the communication request after determining that the second one of the one or more processing cores is currently in the active state.

17. The system on a chip node of claim 16 wherein:

the one or more power management portions assess the second one of the one or more processing cores to determine an available processing power capacity prior to causes the communication request to be delivered to the second one of the one or more processing cores; and

the one or more power management portions cause the communication request to be delivered to the second one of the one or more processing cores in response to determining that the second one of the one or more processing cores has sufficient processing power available for performing the task to be initiated by the communication request.

18. The system on a chip node of claim 17, further comprising:

one or more management processors coupled to the fabric switch and to each one of the one or more processing cores, wherein the one or more management processors comprise the one or more power management portions.

19. The system on a chip node of claim 10, further comprising:

one or more management processors coupled to the fabric switch and to each one of the one or more processing cores, wherein the one or more management processors comprises the one or more power management portions.