GROUP III-NITRIDE METAL-INSULATOR-SEMICONDUCTOR HETEROSTRUCTURE FIELD-EFFECT TRANSISTORS

• US 20130099284A1
• Filed: 10/20/2011
• Published: 04/25/2013
• Est. Priority Date: 10/20/2011
• Status: Abandoned Application

• Current Assignee: TriQuint Semiconductor Incorporated (Qorvo, Inc.)
• Original Assignee: TriQuint Semiconductor Incorporated (Qorvo, Inc.)
• Inventors: Tserng, Hua-Quen, Saunier, Paul
• Application Number:
  US13/278,084
• Publication Number:
  US 20130099284A1
• Time in Patent Office: Days
• US Class Current: 257/194
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device such as, for example, a high electron mobility transistor (HEMT) or metal-insulator-semiconductor field-effect transistor (MISFET), or combinations thereof. The IC device includes a buffer layer formed on a substrate, a barrier layer formed on the buffer layer, the barrier layer including aluminum (Al), nitrogen (N), and at least one of indium (In) and gallium (Ga), a cap layer formed on the barrier layer, the cap layer including nitrogen (N) and at least one of indium (In) and gallium (Ga), and a gate formed on the cap layer, the gate being directly coupled with the cap layer. Other embodiments may also be described and/or claimed.

Claims

1. An apparatus comprising:

a buffer layer formed on a substrate;

a barrier layer formed on the buffer layer, the barrier layer including aluminum (Al), nitrogen (N), and at least one of indium (In) or gallium (Ga);

a cap layer formed on the barrier layer, the cap layer including nitrogen (N) and at least one of indium (In) or gallium (Ga); and

a gate formed on the cap layer, the gate being directly coupled with the cap layer.

2. The apparatus of claim 1, wherein:

the cap layer is polycrystalline gallium nitride (GaN) or polycrystalline aluminum nitride (AlN); and

the cap layer has a thickness of 50 Angstroms or less.

3. The apparatus of claim 1, wherein:

the cap layer has a first bandgap energy that is greater than 5 electron volts (eV);

the barrier layer has a second bandgap energy that is less than the first bandgap energy; and

the buffer layer has a third bandgap energy that is less than the second bandgap energy.

4. The apparatus of claim 1, wherein:

the barrier layer is epitaxially coupled with the buffer layer; and

the cap layer is epitaxially coupled with the barrier layer.

5. The apparatus of claim 1, wherein:

the buffer layer includes gallium nitride (GaN); and

the buffer layer has a thickness of 1 micron to 2 microns.

6. The apparatus of claim 5, wherein the barrier layer includes aluminum gallium nitride (Al_xGa_1-xN), where x is a value from 0.15 to 0.3 that represents relative quantities of aluminum and gallium.

7. The apparatus of claim 5, wherein the barrier layer includes indium aluminum nitride (In_yAl_1-yN), where y is a value from 0.13 to 0.21 that represents relative quantities of indium and aluminum.

8. The apparatus of claim 1, wherein the gate extends at least 5 Angstroms into the cap layer.

9. The apparatus of claim 1, wherein:

the cap layer includes a first portion substantially having a single crystal material, the first portion being formed on and directly coupled with the barrier layer; and

the cap layer includes a second portion substantially having a polycrystalline material, the second portion being formed on and directly coupled with the first portion.

10. The apparatus of claim 1, further comprising:

a dielectric layer epitaxially coupled with the cap layer.

11. The apparatus of claim 1, wherein:

the gate is a T-shaped field plate gate; and

the gate includes nickel (Ni), platinum (Pt), iridium (Ir), molybdenum (Mo), or gold (Au).

12. The apparatus of claim 1, further comprising:

a source coupled with the cap layer; and

a drain coupled with the cap layer, wherein each of the source and the drain extend through the cap layer and the barrier layer into the buffer layer, the source is an ohmic contact, the drain is an ohmic contact, and a shortest distance between the drain and the gate is greater than a shortest distance between the source and the gate.

13. The apparatus of claim 12, further comprising:

the substrate, the substrate including silicon (Si), silicon carbide (SiC), sapphire (Al₂O₃), gallium nitride (GaN), or aluminum nitride (AlN);

a dielectric layer formed on the cap layer, the dielectric layer substantially encapsulating the gate; and

a field plate formed on the dielectric layer over the gate, the field plate being electrically coupled with the source.

14. The apparatus of claim 1, wherein:

the cap layer is a gate dielectric such that the gate is capacitively coupled with the barrier layer through the cap layer; and

the gate is part of a high electron mobility transistor (HEMT) switch device for a power amplifier application.

15. A method comprising:

forming a buffer layer on a substrate;

forming a barrier layer on the buffer layer, the barrier layer including aluminum (Al), nitrogen (N), and at least one of indium (In) or gallium (Ga);

forming a cap layer on the barrier layer, the cap layer including nitrogen (N) and at least one of indium (In) or gallium (Ga); and

forming a gate on the cap layer, the gate being directly coupled with the cap layer.

16. The method of claim 15, wherein each of the buffer layer, the barrier layer, and the cap layer is formed by epitaxial deposition using molecular beam epitaxy (MBE), atomic layer epitaxy (ALE), chemical beam epitaxy (CBE) or metal-organic chemical vapor deposition (MOCVD).

17. The method of claim 15, wherein:

the cap layer is formed by epitaxially depositing gallium nitride (GaN) or aluminum nitride (AlN) at a temperature from 500°

C. to 600°

C.; and

the cap layer is formed to have a thickness of 50 Angstroms or less.

18. The method of claim 15, wherein:

the cap layer has a first bandgap energy that is greater than 5 electron volts (eV);

the barrier layer has a second bandgap energy that is less than the first bandgap energy; and

the buffer layer has a third bandgap energy that is less than the second bandgap energy.

19. The method of claim 15, wherein:

the barrier layer is formed by epitaxially depositing the barrier layer on the buffer layer; and

the cap layer is formed by epitaxially depositing the cap layer on the barrier layer.

20. The method of claim 15, further comprising:

forming a source and a drain on the cap layer;

forming a dielectric layer to substantially encapsulate the gate; and

forming a field plate on the dielectric layer, the field plate being disposed over the gate.