GALLIUM ARSENIDE HETEROJUNCTION SEMICONDUCTOR STRUCTURE

• US 20130099287A1
• Filed: 10/19/2012
• Published: 04/25/2013
• Est. Priority Date: 10/20/2011
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Moser, Brian G., Fresina, Michael T.
• Granted Patent: US 9,761,678 B2
• Time in Patent Office: Days
• US Class Current: 257/197
• CPC Class Codes: A61P 11/06 Antiasthmatics
• CPC Class Codes: A61P 37/02 Immunomodulators
• CPC Class Codes: H01L 29/0817 of heterojunction bipolar transistors H01L29/7375 takes precedence
• CPC Class Codes: H01L 29/201 including two or more compounds , e.g. alloys H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/207 further characterised by the doping material H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/41708 Emitter or collector electrodes for bipolar transistors
• CPC Class Codes: H01L 29/42304 Base electrodes for bipolar transistors
• CPC Class Codes: H01L 29/66318 Heterojunction transistors
• CPC Class Codes: H01L 29/7371 Vertical transistors

Abstract

Embodiments of semiconductor structure are disclosed along with methods of forming the semiconductor structure. In one embodiment, the semiconductor structure includes a semiconductor substrate, a collector layer formed over the semiconductor substrate, a base layer formed over the semiconductor substrate, and an emitter layer formed over the semiconductor substrate. The semiconductor substrate is formed from Gallium Arsenide (GaAs), while the base layer is formed from a Gallium Indium Nitride Arsenide Antimonide (GaInNAsSb) compound. The base layer formed from the GaInNAsSb compound has a low bandgap, but a lattice that substantially matches a lattice constant of the underlying semiconductor substrate formed from GaAs. In this manner, semiconductor devices with lower base resistances, turn-on voltages, and/or offset voltages can be formed using the semiconductor structure.

Claims

1. A semiconductor structure comprising:

a semiconductor substrate formed from Gallium Arsenide (GaAs);

a collector layer formed over the semiconductor substrate;

a base layer formed over the semiconductor substrate and formed from a Gallium Indium Nitride Arsenide Antimonide (GaInNAsSb) compound; and

an emitter layer formed over the semiconductor substrate.

2. The semiconductor structure of claim 1 wherein the base layer is epitaxial such that the GaInNAsSb compound is a GaInNAsSb crystal.

3. The semiconductor structure of claim 2 wherein the GaInNAsSb crystal has a non-stochiometric formula of Ga_1-xIn_xN_yAs_1-y-zSb_z, 0.07≦

x≦

0.18, 0.025≦

y≦

0.04, 0.001≦

z≦

0.03.

4. The semiconductor structure of claim 1 wherein the collector layer, the base layer, and the emitter layer are formed so as to be substantially parallel to one another.

5. The semiconductor structure of claim 4 wherein:

the semiconductor substrate is formed from a GaAs crystal having a first lattice constant; and

the GaInNAsSb crystal has a second lattice constant that substantially matches the first lattice constant of the GaAs crystal.

6. The semiconductor structure of claim 5 wherein:

the collector layer is epitaxial so as to be formed from a third crystal having a third lattice constant that substantially matches the first lattice constant of the GaAs crystal;

the emitter layer is epitaxial so as to be formed from a fourth crystal having a fourth lattice constant that substantially matches the first lattice constant of the GaAs crystal.

7. The semiconductor structure of claim 6 wherein:

the fourth crystal of the emitter layer is selected from a group consisting of an Aluminum Gallium Arsenide (AlGaAs) crystal and a Indium Gallium Phosphide (InGaP) crystal; and

the emitter layer is further formed on the base layer to provide a first heterojunction between the emitter layer and the base layer.

8. The semiconductor structure of claim 7 wherein the base layer has a bandgap between approximately 0.92 electron volts (eV) and 1.04 eV.

9. The semiconductor structure of claim 8 wherein:

the third crystal of the collector layer is selected from a group consisting of an AlGaAs crystal, an InGaP crystal, and another GaAs crystal; and

the base layer is further formed on the collector layer to provide a second heterojunction between the collector layer and the base layer, wherein a second bandgap at the second heterojunction is less than the first bandgap at the first heterojunction.

10. The semiconductor structure of claim 1 wherein:

the base layer is epitaxial such that the GaInNAsSb compound is a GaInNAsSb crystal doped such that the base layer is p-type;

the collector layer is epitaxial so as to be formed from a second crystal, the second crystal being doped so that the collector layer is n-type; and

the emitter layer is epitaxial so as to be formed from a third crystal, the third crystal being doped so that the emitter layer is n-type.

11. The semiconductor structure of claim 10 wherein a heterojunction bipolar transistor (HBT) is formed with the semiconductor structure, the HBT comprising:

an emitter terminus operably associated with the emitter layer so that an emitter of the HBT is provided by the emitter layer;

a base terminus operably associated with the base layer so that a base of the HBT is provided by the base layer; and

a collector terminus operably associated with the collector layer so that a collector of the HBT is provided by the collector layer.

12. The semiconductor structure of claim 10 wherein the GaInNAsSb crystal is doped with a p-type dopant such that the base layer is p-type, the p-type dopant having a concentration of approximately between 1×

10¹⁹ molecules and 1×

10²⁰ molecules of the p-type dopant per cubic centimeter of the GaInNAsSb crystal.

13. The semiconductor structure of claim 12 wherein a thickness of the base layer is in a range of between approximately 500 angstroms and 2000 angstroms.

14. The semiconductor structure of claim 10 further comprising:

an emitter cap layer formed over the emitter layer, the emitter cap layer being epitaxial so as to be formed from a fourth crystal, wherein the fourth crystal is doped so that the emitter cap layer is n-type, but such that doping is at a higher concentration than at the emitter layer; and

a subcollector layer formed beneath the collector layer, the subcollector layer being epitaxial so as to be formed from a fifth crystal, wherein the fifth crystal is doped so that the subcollector layer is n-type, but such that doping is at a higher concentration than at the collector layer.

15. The semiconductor structure of claim 14 wherein:

the second crystal is selected from a group consisting of an Aluminum Gallium Arsenide (AlGaAs) crystal, an Indium Gallium Phosphide (InGaP) crystal, and a GaAs crystal;

the third crystal is selected from a group consisting of an AlGaAs crystal and an InGaP crystal; and

the fourth crystal is an Indium Gallium Arsenide (InGaAs) crystal; and

the fifth crystal is a GaAs crystal.

16. The semiconductor structure of claim 15 wherein:

the semiconductor substrate is formed from a second GaAs crystal having a first lattice constant;

the second crystal has a second lattice constant;

the third crystal has a third lattice constant;

the GaAs crystal that forms the subcollector layer has a fourth lattice constant; and

wherein the second lattice constant, the third lattice constant, and the fourth lattice constant substantially match the first lattice constant.

17. The semiconductor structure of claim 16 further comprising a grading layer wherein:

the grading layer is formed on the emitter layer;

the emitter cap layer is formed on the grading layer;

the InGaAs crystal has a fifth lattice constant; and

the grading layer is configured to provide a grade between the fifth lattice constant of the InGaAs crystal and the third lattice constant of the third crystal.

18. A method of forming a semiconductor structure comprising:

providing a semiconductor substrate formed from Gallium Arsenide (GaAs);

forming a collector layer over the semiconductor substrate;

forming a base layer over the semiconductor substrate such that the base layer is formed from a Gallium Indium Nitride Arsenide Antimonide (GaInNAsSb) compound; and

forming an emitter layer over the semiconductor substrate.

19. The method of claim 18 wherein forming the base layer over the semiconductor substrate comprises growing the base layer epitaxially such that the GaInNAsSb compound is a GaInNAsSb crystal.

20. The method of claim 19 wherein the GaInNAsSb crystal has a non-stochiometric formula of Ga_1-xIn_xN_yAs_1-y-zSb_z, 0.07≦

x≦

0.18, 0.025≦

y≦

0.04, 0.001≦

z≦

0.03.

21. The method of claim 20 wherein:

forming the collector layer over the semiconductor substrate comprises growing the collector layer epitaxially such that the collector layer is formed as a first crystal;

growing the base layer epitaxially such that the GaInNAsSb compound is the GaInNAsSb crystal comprises growing the base layer epitaxially on the collector layer;

forming the emitter layer over the semiconductor substrate comprises growing the emitter layer epitaxially on the base layer such that the emitter layer is formed as a second crystal.

22. The method of claim 21 wherein each of growing the collector layer epitaxially, growing the base layer epitaxially, and growing the emitter layer epitaxially is through Molecular Beam Epitaxy (MBE) deposition.

23. The method of claim 21 wherein each of growing the collector layer epitaxially, growing the base layer epitaxially, and growing the emitter layer epitaxially is through Metalorganic Chemical Vapor Deposition (MOCVD) deposition.

24. The method of claim 18 wherein:

forming the collector layer over the semiconductor substrate comprises growing the collector layer epitaxially over the semiconductor substrate so that the collector layer is formed as a first crystal doped such that the collector layer is n-type, the first crystal being selected from a group consisting of an Aluminum Gallium Arsenide (AlGaAs) crystal, an Indium Gallium Phosphide (InGaP) crystal, and a GaAs crystal;

forming the base layer comprises growing the base layer epitaxially on the collector layer such that the GaInNAsSb compound is a GaInNAsSb crystal doped such that the base layer is p-type; and

forming the emitter layer over the semiconductor substrate comprises growing the emitter layer epitaxially on the base layer such that the emitter layer is formed as a second crystal doped such that the emitter layer is n-type, the second crystal being selected from a group consisting of an AlGaAs crystal and an InGaP crystal.

25. The method of claim 24 further comprising forming a heterojunction bipolar transistor (HBT) wherein forming the HBT comprises:

forming an emitter of the HBT with the emitter layer;

forming a base of the HBT with the base layer;

forming a collector of the HBT with the collector layer.

26. The method of claim 25 wherein:

forming the emitter of the HBT comprises;

providing a first metallic layer over the emitter layer;

removing at least a portion of the first metallic layer so that the first metallic layer is shaped into an emitter terminus operably associated with the emitter layer so as to provide the emitter of the HBT with the emitter layer; and

etching the emitter layer so that the emitter of the HBT has an emitter area and to expose the base layer along a perimeter of the emitter area; and

forming the base of the HBT comprises;

providing a second metallic layer over the base layer;

removing at least a portion of the second metallic layer so that the second metallic layer is shaped into a base terminus operably associated with the base layer so as to provide the base of the HBT with the base layer; and

etching the base layer so that the base of the HBT has a base area and to expose the collector layer along a perimeter of the base area.

27. The method of claim 26 further comprising:

growing a subcollector layer epitaxially on the semiconductor substrate prior to forming the collector layer over the semiconductor substrate so that the subcollector layer is formed as a third crystal doped to be n-type, but such that doping is at a higher concentration than at the collector layer;

wherein forming the collector comprises;

etching the collector layer so that the collector of the HBT has a collector area and to expose the subcollector layer along a perimeter of the collector area;

providing a third metallic layer over the subcollector layer; and

removing at least a portion of the third metallic layer so that the third metallic layer is shaped into a collector terminus operably associated with the collector layer so as to provide the collector of the HBT with the collector layer.