METHOD FOR MANUFACTURING INSULATED-GATE TRANSISTORS

• US 20130099322A1
• Filed: 10/24/2012
• Published: 04/25/2013
• Est. Priority Date: 10/25/2011
• Status: Abandoned Application

• Current Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Inventors: Bianchi, Raul Andres, Perrin, Emmanuel, Bidal, Gregory
• Application Number:
  US13/659,768
• Publication Number:
  US 20130099322A1
• Time in Patent Office: Days
• US Class Current: 257/368
• CPC Class Codes: H01L 21/28229 by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer
• CPC Class Codes: H01L 21/76237 introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Abstract

A method for defining an insulating area in a semiconductor substrate, including a step of forming of a bonding layer on the walls and the bottom of a trench defined in the substrate. A step of passivation of the apparent surface of said bonding layer, at least close to the surface of said semiconductor substrate.

Claims

1. A method for manufacturing MOS transistors, comprising:

forming an insulating area in a semiconductor substrate, the forming including;

forming a trench in a surface of the semiconductor substrate;

forming a bonding layer on walls of the trench; and

passivating at least a portion of the bonding layer; and

forming an insulated gate, on the surface of the substrate and in contact with the insulating area, said gate including a stack of a insulating first layer having a high dielectric constant and a second layer including atoms capable of diffusing towards the first layer.

2. The method of claim 1, wherein the passivating the portion of the bonding layer includes performing a low-power implantation of one of carbon or nitrogen atoms in said bonding layer.

3. The method of claim 1, wherein the passivating the portion of the bonding layer includes depositing a passivation layer over the bonding layer.

4. The method of claim 3, wherein the passivation layer is made of at least one of aluminum oxide, lanthanum oxide, or silicon nitride.

5. The method of claim 1, comprising, following the passivating, filling the trench with an insulating material.

6. The method of claim 1, comprising diffusing atoms of the second layer towards the first layer in an anneal process.

7. A method, comprising:

forming a trench in a substrate of semiconductor material;

forming a bonding layer on walls of the trench;

positioning insulating material in the trench;

forming a transistor gate on a face of the substrate and extending at least as far as an edge of the trench, including;

depositing a first gate layer on the face of the substrate,

depositing a second gate layer on the first gate layer, and

diffusing atoms from the second gate layer to the first gate layer; and

while diffusing the atoms, blocking parasitic diffusion agents that form on surfaces of the bonding layer from affecting the diffusing.

8. The method of claim 7 wherein the blocking the parasitic diffusion agents comprises passivating a portion of the bonding layer by implanting passivation material into a surface of the bonding layer.

9. The method of claim 8 wherein the passivation material comprises atoms of one of carbon and nitrogen.

10. The method of claim 7 wherein the blocking the parasitic diffusion agents comprises forming a passivation layer on the walls of the trench between the bonding layer and the insulating material.

11. The method of claim 7 wherein:

the forming the transistor gate comprises forming a third gate layer on the face of the substrate between the first gate layer and the face of the substrate; and

the diffusing atoms comprises diffusing atoms from the second gate layer toward an interface between the first gate layer and the third gate layer.

12. A device, comprising:

a substrate of semiconductor material;

an insulating trench extending into the substrate from a face of the substrate;

insulating material positioned in the insulating trench;

a bonding layer positioned on walls of the trench and between the walls of the trench and the insulating material, a portion of the bonding layer being passivated;

a MOS device including a channel region positioned in the substrate adjacent to the trench; and

an insulated gate positioned on the face of the substrate, over the channel region, and at least on an edge of the trench.

13. The device of claim 12 wherein the bonding layer includes passivating material implanted into a surface of the bonding layer.

14. The device of claim 12, comprising a passivation layer positioned on the walls of the trench between the bonding layer and the insulating material.

15. The device of claim 12 wherein the insulated gate includes a dielectric layer positioned on the substrate, and a diffusion material layer positioned on the dielectric layer, atoms of the diffusion material layer being positioned on a side of the dielectric layer opposite the diffusion material layer.

16. A device, comprising:

a substrate of semiconductor material;

an insulating trench extending into the substrate from a face of the substrate;

insulating material positioned in the insulating trench;

a bonding layer positioned on walls of the trench between the walls of the trench and the insulating material;

a MOS device including a channel region positioned in the substrate adjacent to the trench;

an insulated gate positioned on the face of the substrate over the channel region and extending at least to an edge of the trench, the insulated gate including a diffusion material layer positioned on the substrate and a dielectric layer positioned on the substrate between the substrate and the diffusion material layer, with atoms of the diffusion material layer positioned on a side of the dielectric layer opposite the diffusion material layer; and

means for blocking parasitic diffusion agents that form on surfaces of the bonding layer from affecting diffusion of the atoms through the dielectric layer.

17. The device of claim 16 wherein the means for blocking comprise a passivating material implanted into a surface of the bonding layer.

18. The device of claim 17 wherein the passivating material comprises atoms of at least one of carbon and nitrogen.

19. The device of claim 16 wherein the means for blocking comprise a passivation layer positioned on the walls of the trench between the bonding layer and the insulating material.

20. The device of claim 19 wherein the passivation layer comprises atoms of at least one of aluminum oxide, lanthanum oxide, or silicon nitride.