METAL GATE STRUCTURE OF A SEMICONDUCTOR DEVICE

• US 20130099323A1
• Filed: 10/20/2011
• Published: 04/25/2013
• Est. Priority Date: 10/20/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: ZHU, Ming, LIN, Hui-Wen, CHUANG, Harry-Hak-Lay, YOUNG, Bao-Ru, CHEN, Ryan Chia-Jen, HUANG, Yuan-Sheng, CHEN, Chao-Cheng
• Granted Patent: US 9,595,443 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate comprising an isolation region surrounding and separating a P-active region and an N-active region; a P-metal gate electrode over the P-active region and extending over the isolation region, wherein the P-metal gate electrode comprises a P-work function metal and an oxygen-containing TiN layer between the P-work function metal and substrate; and an N-metal gate electrode over the N-active region and extending over the isolation region, wherein the N-metal gate electrode comprises an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein the nitrogen-rich TiN layer connects to the oxygen-containing TiN layer over the isolation region.

Claims

1. A complementary metal-oxide-semiconductor (CMOS) semiconductor device comprising:

a substrate comprising an isolation region adjacent to and separating a P-active region and an N-active region;

a P-metal gate electrode over the P-active region and extending over the isolation region, wherein the P-metal gate electrode comprises a P-work function metal and an oxygen-containing TiN layer between the P-work function metal and substrate; and

an N-metal gate electrode over the N-active region and extending over the isolation region, wherein the N-metal gate electrode comprises an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein the nitrogen-rich TiN layer connects to the oxygen-containing TiN layer over the isolation region.

2. The CMOS semiconductor device of claim 1 further comprising an oxygen-containing TaN layer between the oxygen-containing TiN layer and the P-work function metal.

3. The CMOS semiconductor device of claim 1 further comprising a nitrogen-rich TaN layer between the nitrogen-rich TiN layer and the N-work function metal.

4. The CMOS semiconductor device of claim 1 further comprising a nitrogen-containing gate dielectric layer between the nitrogen-rich TiN layer and substrate.

5. The CMOS semiconductor device of claim 1, wherein the N-metal gate electrode has a recess and P-metal gate electrode has a protrusion extending into the recess.

6. The CMOS semiconductor device of claim 1, wherein a ratio of a maximum width of the P-metal gate electrode to a minimum width of the N-metal gate electrode is from about 1.05 to 1.2.

7. The CMOS semiconductor device of claim 1 further comprising an oxygen-containing TaN layer between the N-work function metal and the P-work function metal.

8. The CMOS semiconductor device of claim 1 further comprising a nitrogen-rich TaN layer between the N-work function metal and the P-work function metal.

9. The CMOS semiconductor device of claim 1, wherein the N-work-function metal comprises a metal selected from a group of Ti, Ag, Al, TiAl, TiAlN, TaC, TaCN, TaSiN, Mn, and Zr.

10. The CMOS semiconductor device of claim 1, wherein the P-work-function metal comprises a metal selected from a group of TiN, WN, TaN, and Ru.

11-20. -20. (canceled)

21. A complementary metal-oxide-semiconductor (CMOS) semiconductor device comprising:

a substrate comprising an isolation region separating a P-active region and an N-active region;

a P-metal gate electrode over the P-active region and extending over the isolation region, wherein the P-metal gate electrode comprises a P-work function metal and a doped TiN layer between the P-work function metal and substrate; and

an N-metal gate electrode over the N-active region and extending over the isolation region, wherein the N-metal gate electrode comprises an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein the nitrogen-rich TiN layer contacts the doped TiN layer over the isolation region.

22. The CMOS semiconductor device of claim 21, wherein the doped TiN layer comprises an oxygen-containing TiN layer or a fluorine-containing TiN layer.

23. The CMOS semiconductor device of claim 21, wherein a ratio of a width of the P-metal gate to a width of the N-metal gate ranges from about 0.8 to about 1.2.

24. The CMOS semiconductor device of claim 21, wherein the P-metal gate comprises a signal metal over the P-work function metal.

25. The CMOS semiconductor device of claim 21, wherein the N-metal gate comprises a signal metal over the N-work function metal.

26. The CMOS semiconductor device of claim 21, further comprising a high-k dielectric layer between the doped TiN layer and the substrate and between the nitrogen-rich TiN layer and the substrate.

27. The CMOS semiconductor device of claim 21, wherein the P-metal gate comprises a P-barrier layer between the P-work function metal and the doped TiN layer.

28. The CMOS semiconductor device of claim 21, wherein the N-metal gate comprises an N-barrier layer between the N-work function metal and the nitrogen-rich TiN layer.

29. A complementary metal-oxide-semiconductor (CMOS) semiconductor device comprising:

a substrate comprising an isolation region separating a P-active region and an N-active region; and

a gate structure over the substrate, the gate structure comprises;

a P-metal gate electrode extending over the isolation region, wherein the P-metal gate electrode comprises a P-work function metal and a doped TiN layer between the P-work function metal and substrate;

an N-metal gate electrode extending over the isolation region, wherein the N-metal gate electrode comprises an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein the nitrogen-rich TiN layer contacts the doped TiN layer over the isolation region; and

a TaN layer between the P-metal gate electrode and the N-metal gate electrode.

30. The CMOS semiconductor device of claim 29, wherein the TaN layer comprises a nitrogen-rich TaN layer, an oxygen-containing TaN layer or a fluorine-containing TaN layer.