SEMICONDUCTOR PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

• US 20130099375A1
• Filed: 10/19/2012
• Published: 04/25/2013
• Est. Priority Date: 10/19/2011
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: KIM, Jong Hoon
• Granted Patent: US 9,018,759 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

A semiconductor package substrate including a substrate body having a front surface configured for mounting a semiconductor chip on the front surface and a rear surface facing the front surface and comprising a window passing through the front and rear surfaces, the window having one or more surfaces inclined from the front surface toward the rear surface; and a conductive pattern arranged along an inclined surface of the window so as to extend from the front surface to the rear surface of the substrate body.

Claims

1. A semiconductor package substrate comprising:

a substrate body having a front surface on which a semiconductor chip is mounted and a rear surface facing the front surface and comprising a window passing through the front and rear surfaces, the window having one or more surfaces inclined from the front surface toward the rear surface; and

a conductive pattern arranged along an inclined surface of the window so as to extend from the front surface to the rear surface of the substrate body.

2. The semiconductor package substrate of claim 1, wherein the inclined surface of the window is formed in such a manner that the window is widened from the front surface toward the rear surface of the substrate body.

3. The semiconductor package substrate of claim 1, wherein the inclined surface of the window is formed in such a manner that the window is narrowed from the front surface toward the rear surface of the substrate body.

4. The semiconductor package substrate of claim 1, wherein the window is formed in a region corresponding to a region where a bonding structure of the semiconductor chip is disposed, such that a path from the bonding structure provided in the semiconductor chip to a system substrate disposed under the semiconductor package substrate becomes as short as possible.

5. The semiconductor package substrate of claim 1, wherein the conductive pattern comprises an extended portion disposed on one or more of the front and rear surfaces of the substrate body.

6. The semiconductor package substrate of claim 1, wherein the conductive pattern comprises Cu or Au.

7. The semiconductor package substrate of claim 1, further comprising a filling material filling at least a part of the window.

8. The semiconductor package substrate of claim 7, wherein the filling material comprises silicon oxide (SiO₂).

9. The semiconductor package substrate of claim 7, wherein the filling material comprises ceramic paste.

10. The semiconductor package substrate of claim 1, further comprising a through-via provided in the substrate body and electrically coupled to a system substrate.

11. The semiconductor package substrate of claim 10, further comprising a power supply terminal disposed on one or more of the front and rear surfaces of the substrate body and coupled to the through-via.

12. The semiconductor package substrate of claim 1, further comprising a first conductive pattern provided on the front surface of the substrate body and coupling a bonding structure formed in the semiconductor chip and the conductive pattern.

13. The semiconductor package substrate of claim 12, wherein the first conductive pattern has substantially the same cross-sectional shape as the conductive pattern.

14. A semiconductor package comprising:

a semiconductor chip; and

a package substrate electrically coupled to the semiconductor chip,

wherein the package substrate comprises;

a substrate body having a front surface on which the semiconductor chip is mounted and a rear surface facing the front surface and comprising a window passing through the front and rear surfaces, the window having one or more surfaces inclined from the front surface toward the rear surface; and

a conductive pattern arranged along an inclined surface of the window so as to extend from the front surface to the rear surface of the substrate body.

15. The semiconductor package of claim 14, wherein the semiconductor chip comprises a bonding structure disposed on a surface coupled to the package substrate.

16. The semiconductor package of claim 15, wherein the bonding structure comprises one or more of a contact pad electrically coupled to the conductive pattern, a pillar bump, and a solder bump.

17. The semiconductor package of claim 15, wherein the bonding structure comprises a contact pad electrically coupled to the conductive pattern, a pillar bump formed over the contact pad, and a solder bump formed over the pillar bump.

18. The semiconductor package of claim 14, wherein the package substrate is electrically coupled to a system substrate through the conductive pattern extended to the rear surface of the package substrate.

19. The semiconductor package of claim 14, wherein the inclined surface of the window is formed in such a manner that the window is widened from the front surface toward the rear surface of the substrate body.

20. The semiconductor package of claim 14, wherein the inclined surface of the window is formed in such a manner that the window is narrowed from the front surface toward the rear surface of the substrate body.

21. The semiconductor package of claim 14, wherein the window is formed in a region corresponding to a region where a bonding structure of the semiconductor chip is disposed, such that a path from the bonding structure provided in the semiconductor chip to a system substrate disposed under the package substrate becomes as short as possible.

22. The semiconductor package of claim 14, wherein the conductive pattern comprises an extended portion disposed on one or more of the front and rear surfaces of the substrate body.

23. The semiconductor package of claim 14, wherein the conductive pattern comprises Cu or Au.

24. The semiconductor package of claim 14, further comprising a filling material filling at least a part of the window.

25. The semiconductor package of claim 14, further comprising a through-via provided in the substrate body and electrically coupled to a system substrate.

26. The semiconductor package of claim 25, further comprising a power supply terminal disposed on one or more of the front and rear surfaces of the substrate and coupled to the through-via.

27. The semiconductor package of claim 14, further comprising a first conductive pattern provided on the front surface of the substrate body and coupling a bonding structure formed in the semiconductor chip and the conductive pattern.

28. The semiconductor package of claim 27, wherein the first conductive pattern has substantially the same cross-sectional shape as the conductive pattern.

29. A semiconductor package substrate comprising:

a substrate body having a front surface configured for mounting a semiconductor chip on the front surface and a rear surface facing the front surface and comprising a window passing through the front and rear surfaces, the window having one or more surfaces inclined from the front surface toward the rear surface; and

a conductive pattern arranged along an inclined surface of the window so as to extend from the front surface to the rear surface of the substrate body.