GYROSCOPE WITH PHASE AND DUTY-CYCLE LOCKED LOOP

• US 20130099836A1
• Filed: 12/22/2011
• Published: 04/25/2013
• Est. Priority Date: 10/25/2011
• Status: Active Grant

• Current Assignee: Invensense Incorporated (TDK Corporation)
• Original Assignee: Invensense Incorporated (TDK Corporation)
• Inventors: Shaeffer, Derek, Soukhaphanith, Ahingsa
• Granted Patent: US 8,884,710 B2
• Time in Patent Office: Days
• US Class Current: 327/148
• CPC Class Codes: G01C 19/5776 Signal processing not specific to any of the devices covered by groups G01C19/5607 - G01C19/5719
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop
• CPC Class Codes: H03L 7/089 the phase or frequency detector generating up-down pulses H03L7/087 takes precedence
• CPC Class Codes: H03L 7/0893 the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop
• CPC Class Codes: Y10T 74/12 Gyroscopes

Abstract

A system and method in accordance with the present invention provides a gyroscope incorporating an improved PLL technique. The improved PLL auto-corrects its own reference low-frequency noise, thereby eliminating this source of noise, improving the noise performance of the gyroscope and allowing a compact implementation. The net result is a gyroscope with improved bias stability that can meet noise requirements with a smaller footprint.

Claims

1. A gyroscope system comprising:

a MEMS gyroscope including a drive-sense terminal and a sense terminal;

a drive amplifier being coupled to the drive-sense terminal;

a sense amplifier being coupled to the sense terminal;

a demodulator including a signal input and a clock input;

a phase-locked loop;

wherein,

the output of the drive amplifier is coupled to an input of the phase-locked loop;

the output of the phase-locked loop is coupled to the clock input;

an output of the sense amplifier is coupled to the signal input;

the MEMS gyroscope is operable to produce a signal at a drive frequency;

the demodulator is operable to demodulate a signal from the MEMS gyroscope;

the phase-locked loop is operable to suppress a phase error determined using both rising and falling edges of the phase-locked loop input.

2. The gyroscope system of claim 1, the PLL further comprising:

a phase-frequency detector (PFD),

a charge pump (CP) coupled to the PFD,

a loop filter (LF) coupled to the CP,

a voltage-controlled oscillator (VCO) coupled to the LF

and a first frequency divider coupled in feedback fashion between the VCO and the PFD.

3. The gyroscope system of claim 1, further comprising:

a phase shifter,

a second frequency divider,

wherein,

the output of the PLL is further coupled to the phase shifter;

the output of the phase shifter is coupled to the second frequency divider;

the second frequency divider is coupled to the clock input of the demodulator;

the phase shifter is programmable to select the number of clock-cycle delays relating its input and output;

the second frequency divider is operable to divide the frequency of the phase shifter output down to the drive frequency.

4. A gyroscope system comprising:

a MEMS gyroscope including a drive-sense terminal and a sense terminal;

a drive amplifier being coupled to the drive-sense terminal;

a sense amplifier being coupled to the sense terminal;

a demodulator including a signal input and a clock input;

a phase- and duty-cycle locked loop (PDCLL);

wherein,

the output of the drive amplifier is coupled to an input of the phase- and duty-cycle locked loop;

the output of the phase- and duty-cycle locked loop is coupled to the clock input;

an output of the sense amplifier is coupled to the signal input;

the MEMS gyroscope is operable to produce a signal at a drive frequency;

the demodulator is operable to demodulate a signal from the MEMS gyroscope;

the phase- and duty-cycle locked loop is operable to suppress a phase error and to suppress a duty-cycle error determined using both rising and falling edges of the phase- and duty-cycle locked loop input.

5. The gyroscope system of claim 4, the PDCLL further comprising:

a phase-frequency and duty-cycle detector (PFDCD),

a charge pump coupled to the PFDCD,

a loop filter coupled to the charge pump and further coupled to the PFDCD input,

the PFDCD further operable to measure a duty-cycle error determined using both rising and falling edges of the phase- and duty-cycle locked loop input.

6. The gyroscope system of claim 5, the PDCLL further comprising:

a second charge pump (CP) coupled to the PFDCD,

a second loop filter (LF) coupled to the second CP,

a voltage-controlled oscillator coupled to the LF,

and a frequency divider coupled in feedback fashion between the voltage-controlled oscillator and the PFDCD,

the PFDCD operable to measure a phase error determined using both rising and falling edges of the phase- and duty-cycle locked loop input.

7. The gyroscope system of claim 4, further comprising:

a phase shifter,

a second frequency divider,

wherein,

the output of the PDCLL is further coupled to the phase shifter;

the output of the phase shifter is coupled to the second frequency divider;

the second frequency divider is coupled to the clock input of the demodulator;

the phase shifter is programmable to select the number of clock-cycle delays relating its input and output;

the second frequency divider is operable to divide the frequency of the phase shifter output down to the drive frequency.

8. A phase- and duty-cycle locked loop (PDCLL) comprising:

a phase locked loop (PLL) comprising a reference clock and a divider clock,

a duty-cycle correction loop, and

a phase-frequency and duty-cycle detector (PFDCD),

wherein,

the PFDCD is operable to measure a phase error and a duty-cycle error between the reference clock and divider clock using both rising and falling edges of both clocks,

the PLL is operable to substantially eliminate the phase error,

the duty-cycle correction loop is operable to substantially eliminate the duty-cycle error.

9. The phase- and duty-cycle locked loop of claim 8, further comprising:

a charge pump (CP) coupled to the PFDCD,

a loop filter (LF) coupled to the charge pump,

a voltage-controlled oscillator (VCO) coupled to the LF,

and a first frequency divider coupled in feedback fashion between the VCO and the PFDCD.

10. The phase- and duty-cycle locked loop of claim 9, further comprising:

a second charge pump coupled to the PFDCD,

a second loop filter coupled to the second charge pump and further coupled to the PFDCD input.

11. A method for simultaneous phase and duty-cycle correction, comprising the steps of:

receiving a reference clock comprising first rising and falling edges;

receiving a divider clock comprising second rising and falling edges;

measuring a first timing error between first and second rising edges;

measuring a second timing error between first and second falling edges;

computing a phase error comprising the sum of the first and second timing errors;

computing a duty-cycle error comprising the difference of the first and second timing errors;

adjusting a clock frequency responsive to the phase error such that the phase error is minimized; and

adjusting a clock duty-cycle responsive to the duty-cycle error such that the duty-cycle error is minimized.

12. A method for gyroscope rate signal demodulation, comprising the steps of:

receiving a drive-sense signal from a MEMS gyroscope;

receiving a sense signal from a MEMS gyroscope;

generating a reference clock comprising first rising and falling edges from the drive-sense signal;

generating an output clock with a frequency proportional to the drive-sense signal frequency;

generating a divider clock comprising second rising and falling edges from the output clock;

measuring a first timing error between first and second rising edges;

measuring a second timing error between first and second falling edges;

computing a phase error comprising the sum of the first and second timing errors;

computing a duty-cycle error comprising the difference of the first and second timing errors;

adjusting a clock frequency responsive to the phase error such that the phase error is minimized;

adjusting a clock duty-cycle responsive to the duty-cycle error such that the duty-cycle error is minimized;

demodulating the sense signal using a clock signal derived from the output clock.

13. The method of claim 12, further comprising the steps of:

delaying the output clock by a number of clock cycles to produce a delayed output clock;

dividing the frequency of the delayed output clock to produce a demodulator clock, such that the frequency of the demodulator clock equals the frequency of the drive-sense signal and the demodulator clock is phase-shifted relative to the drive-sense signal.