SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME FOR ESD PROTECTION

• US 20130100561A1
• Filed: 10/20/2011
• Published: 04/25/2013
• Est. Priority Date: 10/20/2011
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Heubi, Alexander, Senouci, Noureddine
• Granted Patent: US 8,649,137 B2
• Time in Patent Office: Days
• US Class Current: 361/56
• CPC Class Codes: H01L 27/0285 bias arrangements for gate electrode of field effect transistors, e.g. RC networks, voltage partitioning circuits H01L27/0281 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02H 9/046 responsive to excess voltage appearing at terminals of integrated circuits protection by specific structural integration design H01L27/0248

Abstract

In an embodiment a circuit provides protection against electrostatic discharge (ESD). A shunt device is controlled to provide a current bypass upon the occurrence of an ESD event. A trigger circuit controls operation of the shunt device and includes an inverter and a hysteresis means to prevent oscillation of the trigger circuit. A reference is used to trigger the control circuit and has a time constant associated with it to distinguish between power up events and ESD events.

Claims

7. A method of forming a semiconductor device, comprising:

forming an inverter including a p-type transistor and an n-type transistor coupled in series and having an inverter control node and an inverter output node, the p-type transistor further coupled to a positive voltage rail;

forming a trailing transistor coupled between the n-type transistor of the inverter and a negative voltage rail, and forming a trailing node between the trailing transistor and the n-type transistor of the inverter;

forming a clamp transistor coupled between the positive and negative voltage rails and having a clamp control node coupled to the inverter output node;

forming a latching transistor having a latching control node coupled the inverter output node, the latching transistor further coupled in series between a resistance and the trailing node, where the resistance is further coupled to the positive voltage rail; and

forming a resistor-capacitor (RC) circuit coupled in series between the positive and negative voltage rails and including a resistor and a capacitor, with the resistor coupled to the positive voltage rail and the capacitor coupled to the negative rail, an RC node defined by a junction of the resistor and capacitor, and wherein the RC node is coupled to the inverter control node.

8. The method of claim 7, further comprising forming at least one diode coupled in parallel with the capacitor.

9. The method of claim 8, wherein the at least one diode is formed by a plurality of series-connected diodes having a number of diodes, where the number of diodes is selected to limit a maximum voltage across the capacitor.

10. The method of claim 7, wherein the capacitor is formed with a metallic-oxide semiconductor field effect transistor having a gate, a drain, and a source, wherein the gate is connected to the resistor and the drain and source are both connected to the negative voltage rail.

11. The method of claim 7, wherein the resistor and capacitor of the RC circuit are formed to have a resistance value and a capacitance value, respectively, which defines an RC time constant, wherein the resistance and capacitor values are selected such that the RC time constant prevents activation of the clamp transistor during power up events, where the power up events have a slower voltage rise time compared to an ESD event, and wherein the RC time constant causes actuation of the clamp transistor during an ESD event.

12. The method of claim 7, wherein the latching transistor and the trailing transistor are each formed to produce a hysteresis effect controlled by the size proportion of the latching transistor to the trailing transistor.

13. An integrated circuit, comprising:

a voltage differentiator circuit that tracks an input voltage between a positive input and a negative input to the integrated circuit and provides an output based on the input voltage that is time delayed by a preselected time constant;

an inverter coupled to the output of the voltage differentiator circuit and responsive to a difference between the output of the voltage differentiator circuit and the input voltage, the inverter having an inverter output;

a clamp device coupled between the positive input and the negative input and having an input coupled to the inverter output and responsive to the inverter output; and

a fast switch and hysteresis control circuit including a trailing transistor coupled in series with the inverter and a latching transistor coupled between the positive input and a positive side of the trailing transistor.

1. A semiconductor device, comprising:

an inverter including a p-type transistor and an n-type transistor coupled in series and having an inverter control node and an inverter output node, the p-type transistor further coupled to a positive voltage rail;

a trailing transistor coupled between the n-type transistor of the inverter and a negative voltage rail, and forming a trailing node between the trailing transistor and the n-type transistor of the inverter;

a clamp transistor coupled between the positive and negative voltage rails and having a clamp control node coupled to the inverter output node;

a latching transistor having a latching control node coupled the inverter output node, the latching transistor further coupled in series between a resistance and the trailing node, where the resistance is further coupled to the positive voltage rail; and

a resistor-capacitor (RC) circuit coupled in series between the positive and negative voltage rails and including a resistor and a capacitor, with the resistor coupled to the positive voltage rail and the capacitor coupled to the negative rail, an RC node defined by a junction of the resistor and capacitor, and wherein the RC node is coupled to the inverter control node.

2. The semiconductor device of claim 1, further comprising at least one diode coupled in parallel with the capacitor.

3. The semiconductor device of claim 2, wherein the at least one diode is a plurality of series-connected diodes having a number of diodes, where the number of diodes is selected to limit a maximum voltage across the capacitor.

4. The semiconductor device of claim 1, wherein the capacitor is a metallic-oxide semiconductor field effect transistor having a gate, a drain, and a source, wherein the gate is connected to the resistor and the drain and source are both connected to the negative voltage rail.

5. The semiconductor device of claim 1, wherein the resistor and capacitor of the RC circuit have a resistance value and a capacitance value, respectively, defining an RC time constant, wherein the resistance and capacitor values are selected such that the RC time constant prevents activation of the clamp transistor during power up events, where the power up events have a slower voltage rise time compared to an ESD event, and wherein the RC time constant causes actuation of the clamp transistor during an ESD event.

6. The semiconductor device of claim 1, wherein the latching transistor and the trailing transistor produce a hysteresis effect controlled by the size proportion of the latching transistor to the trailing transistor.

14. The integrated circuit of claim 13, further comprising at least one diode coupled between the output of the voltage differentiator circuit and the negative input.

15. The semiconductor device of claim 14, wherein the at least one diode is a plurality of series-connected diodes having a number of diodes, where the number of diodes is selected to limit a maximum voltage between the output of the voltage differentiator circuit and the negative input.

16. The semiconductor device of claim 15, wherein the resistor and capacitor of the RC circuit have a resistance value and a capacitance value, respectively, defining an RC time constant, wherein the resistance and capacitor values are selected such that the RC time constant prevents activation of the clamp transistor during power up events, where the power up events have a slower voltage rise time compared to an ESD event, and wherein the RC time constant causes actuation of the clamp transistor during an ESD event.

17. The semiconductor device of claim 13, wherein the latching transistor and the trailing transistor produce a hysteresis effect controlled by the size proportion of the latching transistor to the trailing transistor.

15-1. The semiconductor device of claim 13, wherein the voltage differentiator circuit includes a series RC circuit with a resistor coupled to the positive input and a capacitor coupled to the negative input, and a junction of the resistor and capacitor forming the output of the voltage differentiator circuit, the capacitor is a metallic-oxide semiconductor field effect transistor having a gate, a drain, and a source, wherein the gate is connected to the resistor and the drain and source are both connected to the negative input.