SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF

• US 20130100723A1
• Filed: 10/18/2012
• Published: 04/25/2013
• Est. Priority Date: 10/24/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Takemura, Yasuhiko
• Granted Patent: US 8,913,419 B2
• Time in Patent Office: Days
• US Class Current: 365/72
• CPC Class Codes: G11C 11/4063 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 2207/002 Isolation gates, i.e. gates coupling bit lines to the sense amplifier
• CPC Class Codes: G11C 2207/005 Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals

Abstract

A semiconductor memory device in which capacitance of a capacitor is lower and integration degree is higher. A plurality of memory blocks is connected to one bit line BL_m. A memory block MB_n_m includes a sub bit line SBL_n_m, a write switch, and a plurality of memory cells. A sub bit line SBL_n+1_m adjacent to the sub bit line SBL_n_m is connected to an amplifier circuit AMP_n/n+1_m including two inverters and two selection switches. A circuit configuration of the amplifier circuit can be changed with the selection switches. The amplifier circuit is connected to the bit line BL_m through a read switch. Because of a sufficiently low capacitance of the sub bit line SBL_n_m, potential change due to electric charges of the capacitor in each memory cell can be amplified by the amplifier circuit AMP_n/n+1_m without an error, and the amplified data can be output to the bit line BL_m.

Claims

1. A semiconductor memory device comprising:

a bit line;

four or more word lines;

a first sub bit line;

a second sub bit line;

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a first inverter, wherein an output terminal of the first inverter is electrically connected to the bit line through the first transistor;

a second inverter, wherein an output terminal of the second inverter is electrically connected to the bit line through the second transistor; and

a first memory block and a second memory block each including two or more memory cells,

wherein the first memory block is electrically connected to the first sub bit line and the second memory block is electrically connected to the second sub bit line,

wherein the first sub bit line is electrically connected to an input terminal of the first inverter and the third transistor,

wherein the output terminal of the first inverter is electrically connected to the second sub bit line through the fourth transistor,

wherein the second sub bit line electrically connected to the second memory block is electrically connected to an input terminal of the second inverter, and

wherein the output terminal of the second inverter is electrically connected to the first sub bit line through the third transistor.

4. The semiconductor memory device according to claim 1, further comprising a first selection transistor and a second selection transistor,

wherein the first selection transistor is electrically connected to the bit line and the first sub bit line, and

wherein the second selection transistor is electrically connected to the bit line and the second sub bit line.

6. The semiconductor memory device according to claim 1, further comprising a selection transistor and a transistor provided in two or more memory cells,

wherein a semiconductor used for the selection transistor of one of the first memory block and the second memory block is different from a semiconductor used for the transistor in one of two or more memory cells.

9. The semiconductor memory device according to claim 1, further comprising a transistor provided in two or more memory cells,

wherein in the first memory block and the second memory block, the transistor in one of two or more memory cells is provided in a different layer from a transistor of another memory cell.

12. The semiconductor memory device according to claim 1, wherein the first inverter and the second inverter are complementary inverters.

15. The semiconductor memory device according to claim 1, wherein a BOC structure is employed.

18. A method for driving the semiconductor memory device according to claim 1, wherein in a period during which only one of the first transistor and the second transistor is in an on state, one of the third transistor and the fourth transistor is turned on.

2. A semiconductor memory device comprising:

a first bit line;

a second bit line;

four or more word lines;

a first sub bit line;

a second sub bit line;

a third sub bit line;

a fourth sub bit line;

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor;

a first inverter, wherein an output terminal of the first inverter is electrically connected to the second bit line through the first transistor;

a second inverter, wherein an output terminal of the second inverter is electrically connected to the first bit line through the second transistor;

a first memory block;

a second memory block;

a third memory block; and

a fourth memory block,

wherein the first memory block, the second memory block, the third memory block, and the forth memory block each include two or more memory cells,

wherein the first memory block, the second memory block, the third memory block, and the fourth memory block are electrically connected to the first sub bit line, the second sub bit line, the third sub bit line, and the fourth sub bit line, respectively,

wherein the first sub bit line is electrically connected to an input terminal of the first inverter through the third transistor,

wherein the second sub bit line is electrically connected to the input terminal of the first inverter through the fourth transistor,

wherein the third sub bit line is electrically connected to an input terminal of the second inverter through the fifth transistor, and

wherein the forth sub bit line is electrically connected to the input terminal of the second inverter through the sixth transistor.

5. The semiconductor memory device according to claim 2, further comprising a first selection transistor, a second selection transistor, a third selection transistor, and a fourth selection transistor,

wherein the first selection transistor is electrically connected to the first bit line and the first sub bit line,

wherein the second selection transistor is electrically connected to the first bit line and the second sub bit line,

wherein the third selection transistor is electrically connected to the second bit line and the third sub bit line, and

wherein the fourth selection transistor is electrically connected to the second bit line and the fourth sub bit line.

7. The semiconductor memory device according to claim 2, further comprising a selection transistor and a transistor provided in two or more memory cells,

wherein a semiconductor used for the selection transistor of one of the first memory block, the second memory block, the third memory block, and the fourth memory block is different from a semiconductor used for the transistor in one of two or more memory cells.

10. The semiconductor memory device according to claim 2, further comprising a transistor provided in two or more memory cells,

wherein in the first memory block, the second memory block, the third memory block, and the fourth memory block, the transistor in one of two or more memory cells is provided in a different layer from a transistor of another memory cell.

13. The semiconductor memory device according to claim 2, wherein the first inverter and the second inverter are complementary inverters.

16. The semiconductor memory device according to claim 2, wherein a BOC structure is employed.

19. A method for driving the semiconductor memory device according to claim 2, wherein in a period during which only one of the first transistor and the second transistor is in an on state, one of the third transistor and the fourth transistor is turned on.

3. A semiconductor memory device comprising:

a bit line;

a sub bit line;

two or more memory cells each including a transistor and a capacitor;

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a first inverter provided between the first transistor and the fourth transistor; and

a second inverter provided between the second transistor and the third transistor and between the third transistor and the fourth transistor,

wherein the sub bit line is electrically connected to the bit line through the third transistor and the first transistor, and

wherein the first transistor and the second transistor are configured so that one of the first transistor and the second transistor is in an on state when the other of the first transistor and the second transistor is in an off state.

8. The semiconductor memory device according to claim 3, further comprising:

a first memory block;

a second memory block; and

a selection transistor provided in one of the first memory block and the second memory block,

wherein a semiconductor used for the selection transistor of one of the first memory block and the second memory block is different from a semiconductor used for the transistor in one of two or more memory cells.

11. The semiconductor memory device according to claim 3, further comprising a first memory block and a second memory block each including two or more memory cells,

wherein in the first memory block and the second memory block, the transistor in one of two or more memory cells is provided in a different layer from a transistor of another memory cell.

14. The semiconductor memory device according to claim 3, wherein the first inverter and the second inverter are complementary inverters.

17. The semiconductor memory device according to claim 3, wherein a BOC structure is employed.

20. A method for driving the semiconductor memory device according to claim 3, wherein in a period during which only one of the first transistor and the second transistor is in an on state, one of the third transistor and the fourth transistor is turned on.