SYSTEM AND METHOD FOR MRAM HAVING CONTROLLED AVERAGABLE AND ISOLATABLE VOLTAGE REFERENCE

• US 20130100725A1
• Filed: 10/21/2011
• Published: 04/25/2013
• Est. Priority Date: 10/21/2011
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Kim, Jung Pill, Kim, Taehyun
• Granted Patent: US 8,675,390 B2
• Time in Patent Office: Days
• US Class Current: 365/148
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0038 Power supply circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 29/026 in sense amplifiers
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/08 Control thereof

Abstract

A memory has a plurality of non-volatile resistive (NVR) memory arrays, each with an associated reference voltage generating circuit coupled by a reference circuit coupling link to a reference line, the reference coupled to a sense amplifier for that NVR memory array. Reference line coupling links couple the reference lines of different NVR memory arrays. Optionally, different ones of the reference coupling links are removed or opened, obtaining respective different average and isolated reference voltages on the different reference lines. Optionally, different ones of the reference circuit coupling links are removed or opened, obtaining respective different averaged voltages on the reference lines, and uncoupling and isolating different reference circuits.

Claims

1. A Non-Volatile Resistive memory comprising:

a plurality of reference cells associated with at least one array of bitcells (I/O), wherein at least two of the plurality of reference cells are coupled to a common node; and

a plurality of sense amplifiers associated with the I/Os, wherein at least one sense amplifier is coupled to the common node.

2. The memory of claim 1, further comprising:

at least one switching device configured to isolate at least one of the plurality of reference cells.

3. The memory of claim 1, further comprising:

at least one switching device configured to isolate at least one of the plurality of reference cells from the common node.

4. The memory of claim 3, further comprising:

at least one switching device configured to isolate at least one of the plurality of reference cells.

5. The memory of claim 3, wherein the isolated reference cell is coupled to its associated I/O.

6. The memory of claim 1, wherein the memory is one of MRAM, STT-MRAM, PRAM, or Resistive RAM.

7. A Non-Volatile Resistive memory comprising:

a first array of bitcells (I/O) having a first reference cell, a first reference cell selectable link from the first reference cell to a first I/O reference line, and a first sense amplifier coupled to the first I/O reference line;

a second I/O having a second reference cell, a second reference cell selectable link from the second reference cell to a second I/O reference line, and a second sense amplifier coupled to the second I/O reference line; and

a reference line coupling link between the first I/O reference line and the second I/O reference line.

8. The memory of claim 7, wherein at least one of the first reference cell selectable link and the second reference cell selectable link is a fusible link capable of being blown to isolate at least one of the first reference cell from the first I/O reference line and the second reference cell from the second I/O reference line.

9. The memory of claim 7, wherein at least one of the first reference cell selectable link and the second reference cell selectable link is a fusible link in a selected, blown state to isolate at least one of the first reference cell from the first I/O reference line and the second reference cell from the second I/O reference line.

10. The memory of claim 7, wherein at least one of the first reference cell selectable link and the second reference cell selectable link is a switchable device capable of being switched to an on state coupling at least one of the first reference cell to the first I/O reference line and the second reference cell to the second I/O reference line, and capable of being switched to an off state to isolate at least one of the first reference cell from the first I/O reference line and the second reference cell from the second I/O reference line.

11. The memory of claim 7, wherein the reference line coupling link is a fusible link coupling the first I/O reference line and the second I/O reference line into a common reference node coupled to the first sensing amplifier and to the second sending amplifier, said fusible link being capable of being blown to destroy the common reference node.

12. The memory of claim 11, wherein at least one of the first reference cell selectable link and the second reference cell selectable link is a fusible link capable of being blown to isolate at least one of the first reference cell from the first I/O reference line and the second reference cell from the second I/O reference line.

13. The memory of claim 12, wherein at least one of the first reference cell selectable link and the second reference cell selectable link is a switchable device capable of being switched to an on state coupling at least one of the first reference cell to the first I/O reference line and the second reference cell to the second I/O reference line, and capable of being switched to an off state to isolate at least one of the first reference cell from the first I/O reference line and the second reference cell from the second I/O reference line.

14. The memory of claim 7, wherein the reference line coupling link is a switchable device capable of being switched on to couple the first I/O reference line and the second I/O reference line into a common reference node coupled to the first sensing amplifier and to the second sending amplifier and of being switched off to remove the common reference node.

15. The memory of claim 14, wherein at least one of the first reference cell selectable link and the second reference cell selectable link is a fusible link capable of being blown to isolate at least one of the first reference cell from the first I/O reference line and the second reference cell from the second I/O reference line.

16. The memory of claim 14, wherein at least one of the first reference cell selectable link and the second reference cell selectable link is a switchable device capable of being switched to an on state coupling at least one of the first reference cell to the first I/O reference line and the second reference cell to the second I/O reference line, and capable of being switched to an off state to isolate at least one of the first reference cell from the first I/O reference line and the second reference cell from the second I/O reference line.

17. The memory of claim 7, further comprising:

a third I/O having a third reference cell, coupled by a third reference cell selectable link to a third I/O reference line, and a third sense amplifier coupled to the third I/O reference line; and

another reference line coupling link between the third I/O reference line and at least one of the first I/O reference line and the second I/O reference line.

18. The memory of claim 17, wherein said reference line coupling link is a first switchable device and said another reference line coupling link is a second switchable device, said first switchable device being capable of being in an on conducting state concurrent with the second switchable device being in an on conducting state to form the first I/O reference line, the second I/O reference line and the third I/O reference line into a first common node coupled to the first sensing amplifier, the second sensing amplifier and the third sensing amplifier.

19. The memory of claim 18, wherein said first switchable device is capable of being in an off non-conducting state concurrent with the second switchable device being in an on conducting state to destroy the first common reference node and form the second I/O reference line and the third reference I/O line into a second common reference node coupled to the second sensing amplifier and the third amplifier and isolated from the first I/O reference line and the first sensing amplifier.

20. The memory of claim 17, wherein said reference line coupling link is a first fusible link and said another reference line coupling link is a second fusible link, to form the first I/O reference line, the second I/O reference line and the third I/O reference line into a first common node.

21. The memory of claim 20, wherein the first fusible link is capable of being in a blown state concurrent with the second fusible link being in a conducting state, to destroy the first common node and form the second I/O reference line and the third reference I/O line into a second common reference node coupled to the second sensing amplifier and the third sensing amplifier and isolated from the first I/O reference line and the first sensing amplifier.

22. The memory of claim 21, wherein the first reference cell selectable link is a first reference cell fusible link, the second reference cell selectable link is a second reference cell fusible link, and the third reference cell selectable link is a third reference cell fusible link.

23. The memory of claim 22, wherein the first reference cell selectable link is capable of being in a blown state concurrent with each of the second reference selectable link and the third reference cell selectable link being in a not blown state, to couple the second reference cell and the third reference cell to the first common reference node concurrent with isolating the first reference cell from the first common reference node.

24. A method for a Non-Volatile Resistive memory comprising:

providing at least one array of bitcells (I/O), each I/O having at least one reference cell having a reference voltage output node and a corresponding I/O reference line;

selecting at least two of the I/O reference lines for a common reference line; and

coupling at least two of the selected I/O reference lines to form a common reference line.

25. The method of claim 24, wherein the selecting comprises:

comparing a voltage at the respective reference voltage output node of at least two of the I/Os to a given acceptable range; and

selecting at least one of the I/O reference lines based, at least in part, on a result of the comparing.

26. The method of claim 24, further comprising:

identifying an acceptability of a voltage at the reference voltage output of the reference cell of at least one of the I/Os, relative to a given range of acceptability; and

isolating at least one of the reference cells based on a result of the identifying an acceptability.

27. The method of claim 26, wherein at least one of the provided I/Os has a conducting link between the PO'"'"'s reference voltage output node and I/O reference line, and wherein at least one isolating includes blowing the conducting link.

28. The method of claim 26, wherein at least one of the provided I/Os has a programmable switch between the I/O'"'"'s reference voltage output node and I/O reference line, and wherein at least one isolating includes programming the programmable switch to an open state.

29. A Non-Volatile Resistive bitcell array memory comprising:

means for generating a first reference voltage;

means for generating a second reference voltage;

means for providing a first sensing reference and a second sensing reference, including means for selectively combining the first reference voltage and the second reference voltage into a common voltage and for selectively providing the common voltage as the first sensing reference, and means for selectively providing the first reference voltage as the first sensing reference;

means for sensing a voltage of a first array of bitcells relative to the first sensing reference; and

means for sensing a voltage of a second array of bitcells relative to the second sensing reference.

30. The memory of claim 29, wherein the means for providing the first sensing reference and the second sensing reference further includes means for selectively providing the second reference voltage as the second sensing reference.

31. The memory of claim 29, wherein the means for providing the first sensing reference and the second sensing reference further includes means for selectively providing the first reference voltage as the second sensing reference.

32. A communication device comprising:

an antenna;

a wireless controller coupled to the antenna;

an integrated circuit coupled to the wireless controller, having

a processing unit,

a Non-Volatile Resistive memory coupled to the processing unit, the memory including

a plurality of reference cells associated with at least one array of bitcells (I/O), wherein at least two of the plurality of reference cells are coupled to a common node, and

a plurality of sense amplifiers associated with the I/Os, wherein at least one sense amplifier is coupled to the common node; and

an input device coupled to the integrated circuit.

33. The device of claim 32, wherein the integrated circuit memory further comprises:

at least one switching device configured to isolate at least one of the plurality of reference cells.

34. The device of claim 32, wherein the integrated circuit memory further comprises:

at least one switching device configured to isolate at least one of the plurality of reference cells from the common node.

35. The device of claim 34, wherein the integrated circuit memory further comprises:

at least one switching device configured to isolate at least one of the plurality of reference cells.

36. The device of claim 34, wherein the isolated reference cell is coupled to its associated I/O.

37. A method for a Non-Volatile Resistive memory comprising steps of:

providing at least one array of bitcells (I/O), each I/O having at least one reference cell having a reference voltage output node and a corresponding I/O reference line;

selecting at least two of the I/O reference lines for a common reference line; and

coupling at least two of the selected I/O reference lines to form a common reference line.

38. The method of claim 37, wherein the step of selecting comprises the steps of:

comparing a voltage at the respective reference voltage output node of at least two of the I/Os to a given acceptable range; and

selecting at least one of the I/O reference lines based, at least in part, on a result of the comparing.

39. The method of claim 37, further comprising steps of:

identifying an acceptability of a voltage at the reference voltage output of the reference cell of at least one of the I/Os, relative to a given range of acceptability; and

isolating at least one of the reference cells based on a result of the identifying an acceptability.

40. The method of claim 39, wherein at least one of the provided I/Os has a conducting link between the I/O'"'"'s reference voltage output node and I/O reference line, and wherein at least one isolating includes blowing the conducting link.

41. The method of claim 39, wherein at least one of the provided I/Os has a programmable switch between the I/O'"'"'s reference voltage output node and I/O reference line, and wherein at least one isolating includes programming the programmable switch to an open state.