SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME
First Claim
1. A semiconductor memory device comprising:
- a first bit line;
a second bit line;
a memory cell connected to one of the first bit line and the second bit line;
an inverter; and
a switch,wherein the inverter is connected to the first bit line and the second bit line via the switch, andwherein an output terminal of the inverter is connected to the switch.
1 Assignment
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Accused Products
Abstract
In a conventional DRAM, data read errors are more likely to occur along with miniaturization of DRAM. A small change in the potential of a first bit line is inverted by a first inverter constituted by an n-channel transistor and a p-channel transistor, and is output to a second bit line through a first selection transistor, which is a first switch. Since the potential of the second bit line is the inverse of the potential of the first bit line, the potential difference between the first bit line and the second bit line is increased. The increased potential difference is amplified by a known sense amplifier, a flip-flop circuit composed of the first inverter and a second inverter (constituted by an n-channel transistor and a p-channel transistor), or the like.
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Citations
20 Claims
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1. A semiconductor memory device comprising:
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a first bit line; a second bit line; a memory cell connected to one of the first bit line and the second bit line; an inverter; and a switch, wherein the inverter is connected to the first bit line and the second bit line via the switch, and wherein an output terminal of the inverter is connected to the switch. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor memory device comprising:
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a first bit line; a second bit line; a memory cell connected to one of the first bit line and the second bit line; a first inverter; a first switch; a second inverter; and a second switch, wherein the first inverter is connected to the first switch, wherein the second inverter is connected to the second switch, wherein the first bit line is connected to the first inverter, wherein the second bit line is connected to the first switch, wherein the first bit line is connected to the second switch, and wherein the second bit line is connected to the second inverter. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A semiconductor memory device comprising:
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a first bit line; a second bit line; a memory cell connected to one of the first bit line and the second bit line; a first inverter; a second inverter; a switch; a first power supply line connected to the first inverter; a second power supply line connected to the first inverter; a third power supply line connected to the second inverter; and a fourth power supply line connected to the second inverter, wherein the first inverter is connected to the first bit line and the second bit line via the switch, and wherein the second inverter is connected to the first bit line and the second bit line. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification