SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME

• US 20130100748A1
• Filed: 10/18/2012
• Published: 04/25/2013
• Est. Priority Date: 10/24/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Takemura, Yasuhiko
• Granted Patent: US 9,230,615 B2
• Time in Patent Office: Days
• US Class Current: 365/189.011
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/08 Control thereof

Abstract

In a conventional DRAM, data read errors are more likely to occur along with miniaturization of DRAM. A small change in the potential of a first bit line is inverted by a first inverter constituted by an n-channel transistor and a p-channel transistor, and is output to a second bit line through a first selection transistor, which is a first switch. Since the potential of the second bit line is the inverse of the potential of the first bit line, the potential difference between the first bit line and the second bit line is increased. The increased potential difference is amplified by a known sense amplifier, a flip-flop circuit composed of the first inverter and a second inverter (constituted by an n-channel transistor and a p-channel transistor), or the like.

Claims

1. A semiconductor memory device comprising:

a first bit line;

a second bit line;

a memory cell connected to one of the first bit line and the second bit line;

an inverter; and

a switch,

wherein the inverter is connected to the first bit line and the second bit line via the switch, and

wherein an output terminal of the inverter is connected to the switch.

2. The semiconductor memory device according to claim 1,

wherein a transistor in the memory cell and a transistor in the inverter are provided in different layers.

3. The semiconductor memory device according to claim 1,

wherein the switch comprises a plurality of transistors.

4. The semiconductor memory device according to claim 1,

wherein the switch comprises transistors with different conductivity types.

5. The semiconductor memory device according to claim 1,

wherein a channel area of an n-channel transistor included in the inverter is from 80% to 125% of a channel area of a p-channel transistor included in the inverter, and

wherein a value obtained by dividing a channel width by a channel length of the p-channel transistor is 2.5 times to 4 times as large as a value obtained by dividing a channel width by a channel length of the n-channel transistor.

6. The semiconductor memory device according to claim 1,

wherein a channel area of an n-channel transistor included in the inverter is 10 F² or larger, where F is the feature size.

7. A method for driving the semiconductor memory device according to claim 1, comprising steps of:

turning on the switch; and

thereafter

amplifying a potential difference between the first bit line and the second bit line.

8. A semiconductor memory device comprising:

a first bit line;

a second bit line;

a memory cell connected to one of the first bit line and the second bit line;

a first inverter;

a first switch;

a second inverter; and

a second switch,

wherein the first inverter is connected to the first switch,

wherein the second inverter is connected to the second switch,

wherein the first bit line is connected to the first inverter,

wherein the second bit line is connected to the first switch,

wherein the first bit line is connected to the second switch, and

wherein the second bit line is connected to the second inverter.

9. The semiconductor memory device according to claim 8,

wherein a transistor in the memory cell and a transistor in the first inverter are provided in different layers.

10. The semiconductor memory device according to claim 8,

wherein the first switch comprises a plurality of transistors.

11. The semiconductor memory device according to claim 8,

wherein the first switch comprises transistors with different conductivity types.

12. The semiconductor memory device according to claim 8,

wherein a channel area of an n-channel transistor included in the first inverter is from 80% to 125% of a channel area of a p-channel transistor included in the first inverter, and

wherein a value obtained by dividing a channel width by a channel length of the p-channel transistor is 2.5 times to 4 times as large as a value obtained by dividing a channel width by a channel length of the n-channel transistor.

13. The semiconductor memory device according to claim 8,

wherein a channel area of an n-channel transistor included in the first inverter is 10 F² or larger, where F is the feature size.

14. A method for driving the semiconductor memory device according to claim 8, comprising steps of:

turning on the first switch; and

thereafter

forming a loop of the first inverter, the first switch, the second inverter, and the second switch by turning on the second switch.

15. A semiconductor memory device comprising:

a first bit line;

a second bit line;

a memory cell connected to one of the first bit line and the second bit line;

a first inverter;

a second inverter;

a switch;

a first power supply line connected to the first inverter;

a second power supply line connected to the first inverter;

a third power supply line connected to the second inverter; and

a fourth power supply line connected to the second inverter,

wherein the first inverter is connected to the first bit line and the second bit line via the switch, and

wherein the second inverter is connected to the first bit line and the second bit line.

16. The semiconductor memory device according to claim 15,

wherein a transistor in the memory cell and a transistor in the first inverter are provided in different layers.

17. The semiconductor memory device according to claim 15,

wherein the switch comprises a plurality of transistors.

18. The semiconductor memory device according to claim 15,

wherein the switch comprises transistors with different conductivity types.

19. The semiconductor memory device according to claim 15,

wherein a channel area of an n-channel transistor included in the first inverter is from 80% to 125% of a channel area of a p-channel transistor included in the first inverter, and

wherein a value obtained by dividing a channel width by a channel length of the p-channel transistor is 2.5 times to 4 times as large as a value obtained by dividing a channel width by a channel length of the n-channel transistor.

20. The semiconductor memory device according to claim 15,

wherein a channel area of an n-channel transistor included in the first inverter is 10 F² or larger, where F is the feature size.