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PROGRAMMABLE, FREQUENCY AGILE DIRECT CONVERSION DIGITAL RECEIVER WITH HIGH SPEED OVERSAMPLING

  • US 20130101074A1
  • Filed: 04/11/2012
  • Published: 04/25/2013
  • Est. Priority Date: 04/11/2011
  • Status: Active Grant
First Claim
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1. A circuit employed in a receiver comprising:

  • a clock;

    an N stage ring counter coupled to said clock;

    an N path switching network;

    at least one predictive coder, wherein a respective one of said at least one predictive coder is coupled to a respective switch of said N path switching network; and

    a digital filter configured to receive an output signal from each of said at least one predictive coder.

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