SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

• US 20130102138A1
• Filed: 10/25/2011
• Published: 04/25/2013
• Est. Priority Date: 10/25/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: YEH, Ming-Hsi, TSAI, Tsung-Chieh, LEE, Chun-Yi
• Granted Patent: US 8,703,594 B2
• Time in Patent Office: Days
• US Class Current: 438/585
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors

Abstract

A method for fabricating a semiconductor device is disclosed. A dummy gate feature is formed between two active gate features in an inter-layer dielectric (ILD) over a substrate. An isolation structure is in the substrate and the dummy gate feature is over the isolation structure. Source/drain (S/D) features are formed at edges of the active gate features in the substrate for forming transistor devices. The disclosed method provides an improved method for reducing parasitic capacitance among the transistor devices. In an embodiment, the improved formation method is achieved by introducing species into the dummy gate feature to increase the resistance of the dummy gate feature.

Claims

1. A method for fabricating a semiconductor device, comprising:

forming a first gate feature and a second gate feature in an inter-layer dielectric (ILD) layer over a substrate, wherein the first and the second gate features have a first resistance;

transforming the first gate feature to a treated gate feature having a second resistance, wherein the second resistance is higher than the first resistance;

removing the second gate feature to form a opening in the ILD layer; and

forming a conductive gate feature in the opening.

2. The method of claim 1, wherein the step of transforming comprises:

performing a treatment on the first gate feature; and

thereafter annealing the substrate.

3. The method of claim 2, wherein the annealing is performed at a temperature ranging between about 700°

C. and about 1000°

C. for a period of time ranging between about 10 sec and about 30 min.

4. The method of claim 2, wherein the treatment introduces oxygen-containing species in the first gate feature.

5. The method of claim 2, wherein the treatment is performed using an ion implantation process.

6. The method of claim 5, wherein the ion implantation process is performed at an energy ranging between about 2 KeV to about 20 KeV with a dosage ranging between about 1E13 atoms/cm² and about 1E17 atoms/cm².

7. The method of claim 1, wherein the conductive gate feature is metal gate.

8. The method of claim 1, wherein the treated gate feature comprises at least 50% volume of silicon oxide.

9. The method of claim 1, wherein the first and the second gate features comprises a poly-silicon gate electrode over a high-k dielectric layer.

10. The method of claim 1, wherein the step of removing the second gate feature is a two-step dry etching process comprising a first step to remove a native oxide film over a poly-silicon film and a second step to remove the poly-silicon film.

11. A method for fabricating a semiconductor device, comprising:

forming a first poly-silicon gate electrode, a second poly-silicon gate electrode, and a third poly-silicon gate electrode over a substrate, wherein the first poly-silicon gate electrode is positioned between the second and the third poly-silicon gate electrodes;

forming an inter-layer dielectric (ILD) within and over the first, the second, and the third poly-silicon gate electrodes;

planarizing the ILD to form a planarized ILD with a surface substantially co-planar with the top surface of the first, the second, and the third poly-silicon gate electrodes;

introducing a species into the first poly-silicon gate electrode;

removing the second and the third poly-silicon gate electrodes to form a first opening and a second opening in the ILD;

forming a first metal gate electrode in the first opening for a p-type metal-oxide-semiconductor (PMOS) device; and

forming a second metal gate electrode in the second opening for an n-type metal-oxide-semiconductor (NMOS) device.

12. The method of claim 11, further comprising:

performing an annealing process after introducing the species in the first poly-silicon gate electrode.

13. The method of claim 12, wherein the annealing process transforms at least a portion of the first poly-silicon gate electrode into silicon oxide.

14. The method of claim 11, wherein the species introduced into the first poly-silicon gate electrode comprises O₂, O₃, CO₂, or combinations thereof.

15. The method of claim 11, wherein the first poly-silicon gate electrode is not removed when removing the second and the third poly-silicon gate electrodes.

16. The method of claim 11, wherein introducing the species is performed using an ion implantation process.

17. The method of claim 16, wherein the ion implantation process is performed at an energy ranging between about 2 KeV to about 20 KeV with a dosage ranging between about 1E13 atoms/cm² and about 1E17 atoms/cm².

18. A method for fabricating a semiconductor device, comprising:

forming a sacrificial gate electrode and a dummy gate electrode over a substrate;

forming an inter-layer dielectric (ILD) within the sacrificial gate electrode and the dummy gate electrode;

transforming the dummy gate electrode into a treated dummy gate electrode with a resistance higher than the resistance of the sacrificial gate electrode or the dummy gate electrode;

removing the sacrificial gate electrode to form a opening in the ILD; and

forming a metal gate electrode in the opening for an active device.

19. The method of claim 18, wherein the step of transforming the dummy gate electrode into the treated dummy gate electrode comprises:

performing a treatment on the dummy gate electrode; and

thereafter annealing the substrate.

20. The method of claim 19, wherein the treatment introduces oxygen-containing species into the dummy gate electrode.