Multi-Processor Architecture Implementing A Serial Switch And Method Of Operating Same
First Claim
1. A multi-processor architecture comprising:
- a plurality of blades, each including;
a plurality of processors, a switch fabric that implements connections using point-to-point serial links, wherein the switch fabric is coupled to each of the plurality of processors, and packet processing logic coupled to the switch fabric; and
a first external switch fabric that implements connections using point-to-point serial links, wherein the first external switch fabric is coupled to each switch fabric of the plurality of blades.
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Accused Products
Abstract
A multi-processor architecture for a network device that includes a plurality of barrel cards, each including: a plurality of processors, a PCIe switch coupled to each of the plurality of processors, and packet processing logic coupled to the PCIe switch. The PCIe switch on each barrel card provides high speed flexible data paths for the transmission of incoming/outgoing packets to/from the processors on the barrel card. An external PCIe switch is commonly coupled to the PCIe switches on the barrel cards, as well as to a management processor, thereby providing high speed connections between processors on separate barrel cards, and between the management processor and the processors on the barrel cards.
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Citations
20 Claims
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1. A multi-processor architecture comprising:
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a plurality of blades, each including;
a plurality of processors, a switch fabric that implements connections using point-to-point serial links, wherein the switch fabric is coupled to each of the plurality of processors, and packet processing logic coupled to the switch fabric; anda first external switch fabric that implements connections using point-to-point serial links, wherein the first external switch fabric is coupled to each switch fabric of the plurality of blades. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method comprising:
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routing a first packet from one of a first plurality of processors through a first switch fabric that implements connections using point-to-point serial links, wherein each of the first plurality of processors and the first switch fabric are located on a first blade; routing a second packet from one of a second plurality of processors through a second switch fabric that implements connections using point-to-point serial links, wherein each of the second plurality of processors and the second switch fabric are located on a second blade; and routing the first packet from the first switch fabric and the second packet from the second switch packet through an external switch fabric that implements connections using point-to-point serial links. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A multi-processor architecture comprising:
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a first plurality of processors; a first switch fabric that implements connections with point-to-point serial links, wherein the first plurality of processors are coupled to the first switch fabric by a first set of point-to-point serial links; a second plurality of processors; a second switch fabric that implements connections with point-to-point serial links, wherein the second plurality of processor are coupled to the first switch fabric by a second set of point-to-point serial links; and a third switch fabric that implements connections with point-to-point serial links, wherein the third switch fabric is coupled to the first switch fabric and the second switch fabric by a third set of point-to-point serial links. - View Dependent Claims (18, 19, 20)
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Specification