SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

• US 20130105813A1
• Filed: 11/01/2012
• Published: 05/02/2013
• Est. Priority Date: 11/02/2011
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: TAKEDA, Hiroshi
• Granted Patent: US 8,748,979 B2
• Time in Patent Office: Days
• US Class Current: 257/76
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Disclosed is a semiconductor device whose breakdown voltage is made high by controlling local concentration of an electric field. A source region faces a second plane, one of side faces of a groove part, and a part thereof extends in a direction in parallel to a nodal line of first and second planes. A drift region faces a third plane being the other side face of the groove part opposite to the second plane with a part thereof extending in a direction parallel to the nodal line of the first plane and the third plane, and is formed at a lower concentration than the source region. The drain region is provided so as to be placed on the other side of the drift region opposite to the groove part and so as to touch the drift region, and is formed at a higher concentration than the drift region.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate whose surface is designated as a first plane;

a groove part provided on the first plane side of the semiconductor substrate;

a source region of a first conductivity type that faces a second plane that is one of side faces of the groove part and at least a part of which extends in a direction parallel to a nodal line of the first plane and the second plane;

a drift region of the first conductivity type that faces a third plane being the other side face of the groove part opposite to the second plane, at least a part of which is provided extending in a direction parallel to a nodal line of the first plane and the third plane, and whose concentration is lower than that of the source region;

a drain region of the first conductivity type that is placed on the other side of the drift region opposite to the groove part and is provided to touch the drift region, and whose concentration is higher than the drift region;

a channel region that is provided over the semiconductor substrate and is sandwiched by the source region and the drift region in a plan view;

a first gate insulating layer provided so as to touch the fourth plane that is a plane lying in a direction that intersects the second plane and the third plane among the side faces of the groove part and so as to touch at least the channel region over the first plane, and

a gate electrode provided over the first gate insulating layer,

wherein the groove part is formed more deeply than the drift region.

2. The semiconductor device according to claim 1, comprising:

a plurality of the groove parts that are arranged serially in a direction parallel to a nodal line of the first plane and the second plane and are provided separated from one another,

wherein the channel region is formed between adjacent groove parts.

3. The semiconductor device according to claim 1, further comprising:

a field plate electrode provided so that it may touch the gate electrode and may overlap the drift region in a plan view,

wherein the film thickness of a part of the first gate insulating layer that touches a top of the drift region is thicker than that of a part thereof that touches a top of the channel region.

4. The semiconductor device according to claim 1,

wherein the gate electrode is provided separated from the third plane of the groove part.

5. The semiconductor device according to claim 4, further comprising:

a second gate insulating layer that touches the third plane and is thicker than the first gate insulating layer.

6. The semiconductor device according to claim 4,

wherein the first gate insulating layer is further provided in contact with the third plane, and

wherein the semiconductor device further comprising a second gate insulating layer that touches the third plane side of the first gate insulating layer.

7. The semiconductor device according to claim 1, further comprising:

an element isolation region that is provided on the first plane side of the semiconductor substrate, is provided to overlap the drift region in a plan view, and is provided separated from the third plane,

wherein the drift region touches the side face on the third plane side and a bottom of the element isolation region.

8. The semiconductor device according to claim 1, further comprising:

an element isolation region provided on the first plane side of the semiconductor substrate,

wherein the depth of the groove part is equal to that of the element isolation region.

9. The semiconductor device according to claim 1,

wherein at least the first plane side of the semiconductor substrate is a group III nitride semiconductor layer, and the source region, the channel region, the drift region, and the drain region are formed in the group III nitride semiconductor layer.

10. The semiconductor device according to claim 9,

wherein the impurity concentration of the channel region is less than or equal to 1×

10<sup>−

16</sup> atoms/cm³.

11. The semiconductor device according to claim 9,

wherein the group III nitride semiconductor layer is an intrinsic semiconductor.

12. The semiconductor device according to claim 9,

wherein the source region, the drift region, and the drain region are n-type, and the n-type impurity is Si.

13. The semiconductor device according to claim 12,

wherein a p-type impurity region is not formed in a portion placed between the source region and the drain region in the group III nitride semiconductor layer.

14. The semiconductor device according to claim 8,

wherein the group III nitride semiconductor layer among layers of the semiconductor substrate is provided over a base substrate, and

the base substrate is a Si substrate, a sapphire substrate, a SiC substrate, or a GaN substrate.

15. The semiconductor device according to claim 8,

wherein a direction that goes from the source region toward the drain region is a [2-1-10] direction or a [01-10] direction.

16. The semiconductor device according to claim 1,

wherein the semiconductor substrate is a Si substrate.

17. The semiconductor device according to claim 16,

wherein a direction that goes from the source region toward the drain region is a [100] direction or a [110] direction.

18. A method of manufacturing a semiconductor device, comprising the steps of:

forming a groove part on a first plane side of a semiconductor substrate;

forming a source region that faces a second plane that is one of side faces of the groove part at a position where at least a part thereof extends in a direction parallel to a nodal line of the first plane and the second plane by implanting impurities of a first conductivity type;

forming a drain region at a position separated from a third plane being the other side face of the groove part opposite to the second plane by implanting impurities of the first conductivity type;

forming a drift region that touches the drain region and faces the third plane at a position where at least a part thereof extends in a direction parallel to a nodal line of the first plane and the third plane by implanting impurities of the first conductivity type whose concentration is lower than those of the source region and the drain region;

forming a first gate insulating layer so that it may touch a fourth plane that is a plane lying in a direction that intersects the second plane and the third plane among the side faces of the groove part and so that it may touch at least a channel region sandwiched by the source region and the drift region in a plan view over the first plane;

after the steps above,

forming a gate electrode over the first gate insulating layer,

wherein the groove part is formed more deeply than the drift region in the groove part formation step.