SEMICONDUCTOR DEVICE

• US 20130105866A1
• Filed: 12/28/2012
• Published: 05/02/2013
• Est. Priority Date: 12/16/2009
• Status: Active Grant

• Current Assignee: Shigeru Kusunoki, Shinichi Ishizawa
• Original Assignee: Shigeru Kusunoki
• Inventors: KUSUNOKI, Shigeru, Ishizawa, Shinichi
• Granted Patent: US 8,847,290 B2
• Time in Patent Office: Days
• US Class Current: 257/272
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors

Abstract

A semiconductor device includes: a rectifying element; an electrode pad electrically connected to the rectifying element; and a resistance and a depletion transistor arranged between the rectifying element and the electrode pad, and electrically connected to each other. The semiconductor device has a configuration in which the rectifying element, the resistance, the depletion transistor, and the electrode pad are serially connected. The semiconductor device is configured to generate a gate potential of the depletion transistor based on a difference in potential across the resistance and to produce a depletion layer in a channel of the depletion transistor based on the gate potential. As a result, a semiconductor device having reasonably large current at low voltage and small current at high voltage can be obtained.

Claims

1. A semiconductor device, comprising:

a rectifying element;

an electrode pad electrically connected to said rectifying element; and

a resistance and a junction-type field effect transistor arranged between said rectifying element and said electrode pad, and electrically connected to each other,

said semiconductor device having a configuration in which said rectifying element, said resistance, said junction-type field effect transistor, and said electrode pad are serially connected, and

said semiconductor device being configured to generate a gate potential of said junction-type field effect transistor based on a difference in potential across said resistance and to produce a depletion layer in a channel of said junction-type field effect transistor based on said gate potential.

2. The semiconductor device according to claim 1, wherein

said junction-type field effect transistor includes an n-channel junction-type field effect transistor, and

said semiconductor device is configured such that a lower potential of a potential of a part of said rectifying element and a potential of said electrode pad is used as said gate potential of said n-channel junction-type field effect transistor.

3. The semiconductor device according to claim 1, wherein

said junction-type field effect transistor includes a p-channel junction-type field effect transistor, and

said semiconductor device is configured such that a higher potential of a potential of a part of said rectifying element and a potential of said electrode pad is used as said gate potential of said p-channel junction-type field effect transistor.

4. The semiconductor device according to claim 1, wherein

said junction-type field effect transistor includes a source, and

said resistance is formed integrally with said channel or said source of said junction-type field effect transistor.

5. The semiconductor device according to claim 1, wherein

said rectifying element includes an anode, and

said electrode pad is an anode electrode pad connected to said anode side.

6. The semiconductor device according to claim 1, wherein

said rectifying element includes a cathode, and

said electrode pad is a cathode electrode pad connected to said cathode side.

7. The semiconductor device according to claim 1, wherein

said junction-type field effect transistor includes a gate, and

said gate of said junction-type field effect transistor is spaced and arranged in a form of a stepping-stone in a width direction of said channel.