Method of fabricating field effect transistor with fin structure and field effect transistor with fin structure fabricated therefrom

• US 20130105867A1
• Filed: 10/31/2011
• Published: 05/02/2013
• Est. Priority Date: 10/31/2011
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Wang, Chih-Jung, Chen, Tong-Yu
• Granted Patent: US 8,871,575 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A method of fabricating a field effect transistor with a fin structure is described. At least a fin structure is formed on a substrate. A planar insulation layer covering the fin structure is formed. A trench is formed in the insulation layer and intersects the fin structure both lengthwise, and thereby an upper portion of the fin structure is exposed to the trench. The exposed upper portion of the fin structure will serve as a gate channel region. A gate structure covering the upper portion is formed within the trench. The upper portion of the fin structure may be further trimmed. Accordingly, the present invention also relates to a field effect transistor with a fin structure, in which, the channel width is less than the source/drain width, and a gate structure has two sidewalls contacting two opposite sidewalls of a source region and a drain region, respectively.

Claims

1. A method of fabricating a field effect transistor with a fin structure, comprising:

providing a substrate;

forming at least one fin structure on the substrate;

forming a planar first insulation layer on the substrate to cover the fin structure;

partially removing the first insulation layer to a depth to form a trench, wherein the trench intersects the fin structure, thereby to expose an upper portion of the fin structure to the trench; and

forming a gate structure covering the exposed upper portion of the fin structure in the trench.

2. The method according to claim 1, further, after forming the trench and before forming the gate structure, comprising:

performing a trim process to reduce a width of the exposed upper portion of the fin structure.

3. The method according to claim 1, wherein, forming the first insulation layer on the substrate comprises steps as follows:

forming a planar second insulation layer on the substrate and covering the fin structure;

partially removing the second insulation layer to the depth to expose the upper portion of the fin structure;

forming an etch stop layer on the second insulation layer and the exposed upper portion of the fin structure; and

forming a third insulation layer covering the etch stop layer.

4. The method according to claim 3, wherein, partially removing the first insulation layer to form the trench comprises:

partially removing the third insulation layer to the etch stop layer to form the trench.

5. The method according to claim 4, further comprising:

removing the etch stop layer in the trench.

6. The method according to claim 1, wherein forming the first insulation layer on the substrate comprises steps as follows:

forming a planar second insulation layer to cover the fin structure;

partially removing the second insulation layer to the depth to expose the upper portion of the fin structure; and

forming a third insulation layer covering the second insulation layer and the exposed upper portion of the fin structure, wherein the third insulation layer and the second insulation layer have different etching rates.

7. The method according to claim 6, wherein, partially removing the first insulation layer to form the trench comprises:

partially etching the third insulation layer to the second insulation layer to form the trench.

8. The method according to claim 1, wherein, forming the gate covering the exposed upper portion of the fin structure in the trench comprises steps as follows:

forming a gate dielectric layer on the fin structure in the trench;

filling the trench with a gate material; and

performing a planarization process on the gate material and the first insulation layer to expose the gate material and the first insulation layer.

9. The method according to claim 8, wherein, the fin structure is further covered with a hard mask layer, and the planarization process is performed to expose the gate material, the first insulation layer and the hard mask layer.

10. The method according to claim 1, wherein, forming the gate structure covering the exposed upper portion of the fin structure in the trench comprises steps as follows:

filling the trench with a sacrificial gate material;

performing a planarization process on the sacrificial gate material and the first insulation layer to expose the sacrificial gate material and the first insulation layer; and

performing a gate structure replacement process to replace the sacrificial gate material with the gate structure.

11. The method according to claim 10, wherein, the fin structure is further covered with a hard mask layer, and the planarization process is performed to expose the sacrificial gate material, the first insulation layer and the hard mask layer.

12. The method according to claim 1, further, after forming the gate, comprising:

removing the rest of the first insulation layer to the depth to expose the gate structure and the fin structure; and

forming a source and a drain in the fin structure at two sides of the gate structure.

13. A field effect transistor with a fin structure comprising:

a substrate comprising at least one fin structure comprising two source/drain regions and a gate channel region between the two source/drain regions;

an isolation structure disposed on the substrate and surrounding the fin structure to expose an upper portion of the fin structure, wherein a width of the gate channel region of the exposed upper portion of the fin structure is less than each of widths of the source region and the drain region; and

a gate structure covering two sidewalls of the gate channel region of the exposed upper portion of the fin structure, wherein two sidewalls of the gate structure contact two facing sidewalls of the two source/drain regions, respectively.

14. The field effect transistor with a fin structure according to claim 13, further comprising a hard mask atop the gate channel region of the fin structure.

15. The field effect transistor with a fin structure according to claim 13, wherein the gate structure further covers a top of the gate channel region of the fin structure.

16. The field effect transistor with a fin structure according to claim 14, wherein the gate structure further covers the hard mask.