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Transistor with Buried P+ and Source Contact

  • US 20130105888A1
  • Filed: 08/10/2012
  • Published: 05/02/2013
  • Est. Priority Date: 08/11/2011
  • Status: Active Grant
First Claim
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1. A transistor comprising:

  • an n-well region implanted into a surface of a substrate;

    a gate region;

    a source region on a first side of the gate region, the source region comprising a p-body region in the n-well region wherein an n+ region and a p+ region are implanted in the p-body region such that the p+ region is below the n+ region; and

    a drain region on a second side of the gate region, the drain region comprising an n+ region.

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