Transistor with Buried P+ and Source Contact

• US 20130105888A1
• Filed: 08/10/2012
• Published: 05/02/2013
• Est. Priority Date: 08/11/2011
• Status: Active Grant

• Current Assignee: Volterra Semiconductor LLC (Analog Devices, Inc.)
• Original Assignee: Volterra Semiconductor Corporation (Analog Devices, Inc.)
• Inventors: Zuniga, Marco A., Lu, Yang, Fatemizadeh, Badredin, Prasad, Jayasimha, Paul, Amit, Ruan, Jun
• Granted Patent: US 10,147,801 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/28105 the final conductor next to the insulator having a lateral composition or doping variation, or being formed laterally by more than one deposition step
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0626 with a localised breakdown region, e.g. built-in avalanching region in self-protected thyristors H01L29/7424
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66696 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

The present application features a transistor that includes an n-well region implanted into a surface of a substrate, a gate region, and a source region, and a drain region. The source region is on a first side of the gate region and includes a p-body region in the n-well region. An n+ region and a p+ region are implanted in the p-body region such that the p+ region is below the n+ region. The drain region is on a second side of the gate region and includes an n+ region.

Claims

1. A transistor comprising:

an n-well region implanted into a surface of a substrate;

a gate region;

a source region on a first side of the gate region, the source region comprising a p-body region in the n-well region wherein an n+ region and a p+ region are implanted in the p-body region such that the p+ region is below the n+ region; and

a drain region on a second side of the gate region, the drain region comprising an n+ region.

2. The transistor of claim 1, comprising a first source electrode in contact with the p+ region and a second source electrode in contact with the n+ region.

3. The transistor of claim 2, wherein the first and second source electrodes are spaced apart along an axis substantially perpendicular to a cell pitch associated with the transistor.

4. The transistor of claim 1, wherein the gate region comprises:

a trench in the n-well region extending from a surface of the n-well region to a first depth, the trench comprising;

a gate of conductive material in the trench, and

dielectric material filling a volume of the trench not filled by the conductive material.

5. The transistor of claim 4, wherein the p-body region comprises a p-type material extending from a surface of the n-well region to a second depth.

6. The transistor of claim 4, wherein at least a portion of the p-body is beneath the trench and extends from a second depth to a third depth, wherein each of the second depth and the third depth is greater than the first depth.

7. The transistor of claim 4, wherein the conductive material comprises polysilicon.

8. The transistor of claim 4, wherein the dielectric material comprises an oxide.

9. The transistor of claim 1, the p-body region comprises a deep p-body region and a shallow p-body region, the shallow p-body region being closer to the surface and having a higher concentration of p-type material than the deep p-body region.

10. The transistor of claim 6, wherein the portion of the p-body beneath the trench is a portion of an epitaxial layer.

11. The transistor of claim 6, wherein the portion of the p-body beneath the trench is a portion of a reduced surface field (RESURF) layer.

12. The transistor of claim 1, wherein a region below the gate between the drain region and the source region provides a channel.

13. The transistor of claim 12, comprising a first plurality of source electrodes in contact with the p+ region and a second plurality of source electrodes in contact with the n+ region.

14. The transistor of claim 13, wherein first and second plurality of source electrodes are arranged on a line.

15. The transistor of claim 14, wherein the line is substantially perpendicular to a direction of current flow through the channel.

16. The transistor of claim 14, wherein the first plurality of source electrodes and the second plurality of source electrodes are arranged in an alternating pattern along the line.