EMBEDDED WAFER LEVEL PACKAGE FOR 3D AND PACKAGE-ON-PACKAGE APPLICATIONS, AND METHOD OF MANUFACTURE

• US 20130105991A1
• Filed: 12/06/2011
• Published: 05/02/2013
• Est. Priority Date: 11/02/2011
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: Stmicroelectronics Pte Limited (STMicroelectronics NV)
• Inventors: Gan, Kah Wee, Huang, Yaohuang, Jin, Yonggang
• Granted Patent: US 8,916,481 B2
• Time in Patent Office: Days
• US Class Current: 257/777
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1041 Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15321 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H05K 1/186 : manufactured by mounting on or connecting to patterned circuits before or during embedding

Abstract

A process for manufacturing a 3D or PoP semiconductor package includes forming a redistribution layer on a reconstituted wafer, then laser drilling a plurality of apertures in the reconstituted wafer, extending from an outer surface of the reconstituted wafer to intersect electrical traces in the first redistribution layer. A solder ball is then positioned adjacent to an opening of each of the apertures. The solder balls are melted and allowed to fill the apertures, making contact with the respective electrical traces and forming a plurality of solder columns. The outer surface of the reconstituted wafer is then planarized, and a second redistribution layer is formed on the planarized surface. The solder columns serve as through-vias, electrically coupling the first and second redistribution layers on opposite sides of the reconstituted wafer.

Claims

1. A method, comprising:

forming a reconstituted wafer by embedding a first semiconductor die in a first molding compound layer, with a face of the die lying substantially in a first plane with a face of the first molding compound layer of the reconstituted wafer;

positioning a first redistribution layer on a first surface of the reconstituted wafer, including forming a first plurality of electrically conductive traces with ones of the first plurality of electrically conductive traces in electrical contact with respective ones of a plurality of circuit contacts positioned on the face of the first semiconductor die;

drilling a first plurality of apertures into the reconstituted wafer, each extending from a second surface of the reconstituted wafer at least as far as a respective one of the first plurality of electrically conductive traces of the first redistribution layer; and

forming, in each of the first plurality of apertures, a respective one of a first plurality of solder columns in electrical contact with the respective one of the first plurality of electrically conductive traces.

2. The method of claim 1 wherein the drilling comprises drilling the first plurality of apertures into the reconstituted wafer, each extending from the second surface of the reconstituted wafer only as far as a respective one of the first plurality of electrically conductive traces

3. The method of claim 1 wherein the forming, in each of the first plurality of apertures, a respective one of a first plurality of solder columns comprises positioning solder on the second surface of the reconstituted wafer adjacent to an opening of each of the first plurality of apertures, and melting the solder positioned on the second surface.

4. The method of claim 3 wherein the positioning solder step comprises positioning a ball of solder on the second surface of the reconstituted wafer adjacent to the opening of each of the first plurality of apertures.

5. The method of claim 3 wherein the positioning solder comprises deposition solder paste on the second surface of the reconstituted wafer adjacent to the opening of each of the first plurality of apertures.

6. The method of claim 3 wherein the forming, in each of the first plurality of apertures, a respective one of a first plurality of solder columns comprises drawing a vacuum around the reconstituted wafer, and releasing the vacuum while the solder is molten.

7. The method of claim 1, comprising:

thinning the reconstituted wafer by removing material from the second surface of the reconstituted wafer to form a third surface of the reconstituted wafer, with an exposed portion of each of the first plurality of solder columns lying in a second plane defined by the third surface;

forming a second redistribution layer on the third surface of the reconstituted wafer, including forming a second plurality of electrically conductive traces, with ones of the second plurality of electrically conductive traces in electrical contact with the exposed portion of respective ones of the first plurality of solder columns.

8. The method of claim 7 wherein the forming a second redistribution layer includes forming a plurality of landing pads, each in electrical contact with a respective one of the second plurality of electrically conductive traces, the method further comprising:

positioning a second semiconductor die over the second redistribution layer; and

forming an electrical connection between each of the plurality of landing pads and a respective one of a plurality of circuit contacts positioned on a face of the second semiconductor die.

9. The method of claim 8, comprising forming a second molding compound layer over the second redistribution layer, thereby encapsulating the second semiconductor die and forming, on a side of the second molding compound layer opposite the second redistribution layer, a fourth surface of the second molding compound layer lying in a third plane that is substantially parallel to the first plane.

10. The method of claim 9, comprising:

drilling a second plurality of apertures in the second molding compound layer, each extending from the fourth surface at least as far as a respective one of the second plurality of electrically conductive traces;

forming, in each of the second plurality of apertures, a respective one of a second plurality of solder columns in electrical contact with the respective one of the second plurality of electrically conductive traces;

thinning the second molding compound layer by removing material from the fourth surface to form a fifth surface of the second molding compound layer, with an exposed portion of each of the second plurality of solder columns lying in a fourth plane defined by the fifth surface;

forming a third redistribution layer on the fifth surface of the second molding compound layer, including forming a third plurality of electrically conductive traces, with ones of the third plurality of electrically conductive traces in electrical contact with the exposed portion of a respective one of the second plurality of solder columns.

11. The method of claim 1 wherein the forming a first redistribution layer comprises forming a plurality of contact pads on a side of the first redistribution layer opposite the reconstituted wafer, with each of the plurality of contact pads in electrical contact with a respective one of the first plurality of electrically conductive traces.

12. The method of claim 11, comprising positioning solder on each of the plurality of contact pads.

13. A process, comprising:

drilling a blind aperture into a reconstituted wafer, the aperture extending from a surface of the reconstituted wafer, through a molding compound layer, and into a first redistribution layer at least as far as a first electrical trace in the first redistribution layer; and

forming a solder column in the blind aperture, with a first end of the solder column in electrical contact with the first electrical trace, and a second end exposed at the surface of the reconstituted wafer.

14. The process of claim 13 wherein the drilling comprises drilling the blind aperture only as far as the first electrical trace.

15. The process of claim 13 wherein the forming comprises:

positioning solder on the surface of the reconstituted wafer adjacent to an opening of the blind aperture; and

melting the solder.

16. The process of claim 15 wherein the forming comprises drawing a vacuum around the reconstituted wafer, and releasing the vacuum while the solder is molten.

17. The process of claim 13, comprising planarizing the reconstituted wafer by removing material from the surface of the reconstituted wafer, so that a face of the solder column lies in a plane defined by a thinned face of the reconstituted wafer.

18. The process of claim 17, comprising forming a second redistribution layer on the thinned face of the reconstituted wafer, including forming a second electrical trace in electrical contact with the face of the solder column.

19. A device, comprising:

a reconstituted wafer having first and second surfaces lying substantially in first and second planes, respectively, the reconstituted wafer including a first molding compound layer and a first semiconductor die embedded in the first molding compound layer, with a face of the die and a face of the first molding compound layer lying substantially in the first plane, the first semiconductor die having a first plurality of circuit contacts positioned on the face of the first semiconductor die;

a first redistribution layer positioned on the first surface of the reconstituted wafer, and including a first plurality of electrically conductive traces with ones of the first plurality of electrically conductive traces in electrical contact with respective ones of the first plurality of circuit contacts; and

a first plurality of substantially cylindrical solder columns, each extending into the reconstituted wafer from the second surface at least as far as a respective one of the first plurality of electrically conductive traces, and in electrical contact therewith.

20. The device of claim 19 wherein each of the first plurality of solder columns extends in the reconstituted wafer from the second surface only as far as the respective one of the first plurality of electrically conductive traces

21. The device of claim 19, comprising a second redistribution layer positioned on the second surface of the reconstituted wafer, and including:

a second plurality of electrically conductive traces, with ones of the second plurality of electrically conductive traces in electrical contact with respective ones of the first plurality of substantially cylindrical solder columns; and

a first plurality of landing pads, each in electrical contact with a respective one of the second plurality of electrically conductive traces.

22. The device of claim 21, comprising a second semiconductor die positioned over the second redistribution layer, with each of the first plurality of landing pads electrically connected to a respective one of a plurality of circuit contacts positioned on a face of the second semiconductor die.

23. The device of claim 22, comprising a second molding compound layer positioned on the second redistribution layer and encapsulating the second semiconductor die, the second molding compound layer having a third surface on a side opposite the second redistribution layer.

24. The device of claim 23, comprising:

a second plurality of substantially cylindrical solder columns, each extending in the second molding compound layer from the third surface at least as far as a respective one of the second plurality of electrically conductive traces, and in electrical contact therewith;

a third redistribution layer positioned on the third surface, and including;

a third plurality of electrically conductive traces, with ones of the third plurality of electrically conductive traces in electrical contact with respective ones of the second plurality of substantially cylindrical solder columns; and

a second plurality of landing pads, each in electrical contact with a respective one of the third plurality of electrically conductive traces.