3D-IC INTERPOSER TESTING STRUCTURE AND METHOD OF TESTING THE STRUCTURE

• US 20130106459A1
• Filed: 10/31/2011
• Published: 05/02/2013
• Est. Priority Date: 10/31/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chi-Yeh, TSENG, Nan-Hsin
• Granted Patent: US 8,680,882 B2
• Time in Patent Office: Days
• US Class Current: 324/759.01
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/5382 Adaptable interconnections, e.g. for engineering changes
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

An interposer for a 3D-IC is provided with a plurality of functional metal wiring segments where the plurality of functional metal wiring segments are connected in series by a plurality of dummy metal wiring segments thus allowing the plurality of functional metal wiring segments to be electrically tested for continuity Each of the plurality of dummy metal wiring segments is provided with a laser fuse portion for disconnecting the dummy metal wiring segments upon completion of the electrical test.

Claims

1. An interposer for a three-dimensional integrated circuit comprising:

a substrate portion provided with a plurality of through substrate vias and having a front surface and a back surface;

a front-side interconnection wiring layers formed on the front surface of the substrate portion, wherein the front-side interconnection wiring layers comprising;

a plurality of functional metal wiring segments; and

an array of μ

Bump pads provided on the top surface of the front-side interconnection wiring layers, wherein each of the functional metal wiring segments connecting two μ

Bump pads;

a plurality of dummy metal wiring segments connecting two or more of the plurality of functional metal wiring segments in series into a chain and the chain terminating in at least two terminal-end μ

Bump pads; and

at least one sacrificial probe pad connected to each of the two terminal-end μ

Bump pads;

wherein each of the plurality of dummy metal wiring segments in the chain is provided with a laser fuse portion for disconnecting the dummy metal wiring segment.

2. The interposer according to claim 1, further wherein the laser fuse portions in a given chain are located within a fuse window.

3. The interposer according to claim 2, wherein the laser fuse portions are aligned parallel to one another and in a side-by-side arrangement for enabling a laser beam to ablate all of the laser fuse portions in the fuse window section in a single pass.

4. The interposer according to claim 1, wherein the dummy metal wiring segments are formed in the front-side interconnect wiring layers at one or more wiring levels within the front-side interconnect wiring layers.

5. The interposer according to claim 1, wherein the surface area of the sacrificial probe pads are larger than the μ

Bump pads by at least 100%.

6. An interposer for a three-dimensional integrated circuit comprising:

a substrate portion provided with a plurality of through substrate vias and having a front surface and a back surface;

a front-side interconnection wiring layers formed on the front surface of the substrate portion, wherein the front-side interconnection wiring layers comprising;

a plurality of functional metal wiring segments; and

an array of μ

Bump pads provided on the top surface of the front-side interconnection wiring layers, wherein each of the functional metal wiring segments connecting two μ

Bump pads;

a plurality of dummy metal wiring segments connecting two or more of the plurality of functional metal wiring segments in series into a chain and the chain terminating in at least two terminal-end μ

Bump pads; and

two sacrificial probe pads connected to each of the two terminal-end μ

Bump pads;

wherein each of the plurality of dummy metal wiring segments in the chain is provided with a laser fuse portion for disconnecting the dummy metal wiring segment.

7. The interposer according to claim 6, further wherein the laser fuse portions in a given chain are located within a fuse window.

8. The interposer according to claim 7, wherein the laser fuse portions are aligned parallel to one another and in a side-by-side arrangement for enabling a laser beam to ablate all of the laser fuse portions in the fuse window section in a single pass.

9. The interposer according to claim 6, wherein the dummy metal wiring segments are formed in the front-side interconnect wiring layers at one or more wiring levels within the front-side interconnect wiring layers.

10. The interposer according to claim 6, wherein the surface area of the sacrificial probe pads are larger than the μ

Bump pads by at least 100%.

11. A method for electrical testing comprising:

providing a 3D-IC interposer in which two or more of a plurality of functional metal wiring segments are connected in series by a plurality of dummy metal wiring segments into a chain, wherein each of the plurality of dummy metal wiring segments in the chain is provided with a laser fuse portion;

performing an electrical continuity testing of the chain; and

laser ablating each of the laser fuse portion.

12. The method according to claim 11, wherein the chain has two ends and at least one sacrificial probe pads are provided at each end of the chain and the step of performing an electrical continuity testing of the chain includes two-point electrical continuity testing of the chain by probing one of the at least one sacrificial probe pads at each end of the chain with electrical test probes.

13. The method according to claim 11, wherein the chain has two ends and two sacrificial probe pads are provided at each end of the chain and the step of performing an electrical continuity testing of the chain includes four-point electrical continuity testing of the chain by probing the two sacrificial probe pads at each end of the chain with electrical test probes.