LEVEL SHIFTER

• US 20130106485A1
• Filed: 10/28/2011
• Published: 05/02/2013
• Est. Priority Date: 10/28/2011
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Mukhopadhyay, Rajarshi, Emerson, Paul M.
• Granted Patent: US 9,270,273 B2
• Time in Patent Office: Days
• US Class Current: 327/333
• CPC Class Codes: H03K 19/017509 Interface arrangements
• CPC Class Codes: H03K 19/018507 Interface arrangements

Abstract

A level shifter is provided. This level shifter includes a first driver, a second driver, a capacitor, and a common mode circuit. The first driver has a first signal path that is coupled between an input terminal and an output terminal, and the first driver operates in a first voltage domain. The second operates in a second voltage domain and includes a second signal path and latch. The second signal path is coupled between an input terminal and an output terminal of the second driver, and the latch that is coupled to the input terminal of the second signal path. The capacitor that is coupled between the output terminal of the first signal path and the input terminal of the second signal path, and the bias circuit is coupled to the input terminal of the second signal path and operates in the second voltage domain.

Claims

1. An apparatus comprising:

a first driver having a first signal path with an input terminal and an output terminal, wherein the first driver operates in a first voltage domain, and wherein the input terminal of the first signal path receives an input signal;

a second driver that operates in a second voltage domain, wherein the second driver has;

a second signal path with an input terminal and an output terminal; and

a latch that is coupled to the input terminal of the second signal path;

a capacitor that is coupled between the output terminal of the first signal path and the input terminal of the second signal path; and

a bias circuit that is coupled to the input terminal of the second signal path and that operates in the second voltage domain.

2. The apparatus of claim 1, wherein the second signal path further comprises a plurality of inverters coupled in series with one another in a sequence between the input and output terminals of the second signal path.

3. The apparatus of claim 2, wherein the capacitor further comprises a first capacitor, and wherein the bias circuit further comprises:

a resistor that is coupled to the input terminal of the second signal path;

a second capacitor; and

a common mode inverter that is coupled between the second capacitor and the resistor.

4. The apparatus of claim 3, wherein the common mode inverter is a replica of the first inverter of the sequence.

5. The apparatus of claim 4, wherein the input signal is differential, and wherein the first driver further comprises a third signal path with an input terminal and an output terminal.

6. The apparatus of claim 5, wherein the resistor further comprises a first resistor, and wherein the second driver further comprises a fourth signal path with an input terminal and an output terminal, and wherein the latch and a second resistor are coupled to the input terminal of the fourth signal path, and wherein the apparatus further comprises a third capacitor that is coupled between the output terminal of the third signal path and the input terminal of the fourth signal path.

7. The apparatus of claim 6, wherein the first and second resistors are coupled together.

8. The apparatus of claim 6, wherein the common mode inverter further comprises a first common mode inverter, and wherein the bias circuit further comprises:

a fourth capacitor; and

a second common mode inverter that is coupled between the second fourth and the second resistor.

9. The apparatus of claim 8, wherein the first and second resistors are adjustable.

10. An apparatus comprising:

a first driver that operates in a first voltage domain, wherein the first driver has;

a first input terminal;

a first output terminal; and

a first set of inverters coupled in series with one another between the first input terminal and the first output terminal;

a second driver that operates in a second voltage domain, wherein the second driver has;

a second input terminal;

a second output terminal;

a second set of inverters coupled in series with one another between the second input terminal and the second output terminal; and

a latch that is coupled to the second input terminal;

a capacitor that is coupled between the first output terminal and the second input terminal; and

a bias circuit that is coupled to the second input terminal and that operates in the second voltage domain.

11. The apparatus of claim 10, wherein the second set of inverters are coupled in series with one another in a sequence, and wherein the capacitor further comprises a first capacitor, and wherein the bias circuit further comprises:

a resistor that is coupled to the second input terminal;

a second capacitor; and

a common mode inverter that is coupled between the second capacitor and the resistor.

12. The apparatus of claim 11, wherein the common mode inverter is a replica of the first inverter of the sequence.

13. The apparatus of claim 12, wherein the first driver further comprises:

a third input terminal;

a third output terminal; and

a third set of inverters coupled in series with one another between the third input terminal and the third output terminal.

14. The apparatus of claim 13, wherein the resistor further comprises a first resistor, and wherein the bias circuit further comprises second resistor, and wherein the second driver further comprises:

a fourth input terminal;

a fourth output terminal that is coupled to the latch and the second resistor; and

a fourth set of inverters coupled in series with one another between the fourth input terminal and the fourth output terminal.

15. The apparatus of claim 14, wherein the apparatus further comprises a third capacitor that is coupled between the third output terminal and the fourth input terminal.

16. The apparatus of claim 15, wherein the first and second resistors are coupled together.

17. The apparatus of claim 15, wherein the common mode inverter further comprises a first common mode inverter, and wherein the bias circuit further comprises:

a fourth capacitor; and

a second common mode inverter that is coupled between the fourth capacitor and the second resistor.

18. The apparatus of claim 17, wherein the first and second resistors are adjustable.