DISPLAY PANEL

• US 20130106677A1
• Filed: 04/09/2012
• Published: 05/02/2013
• Est. Priority Date: 10/26/2011
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Bon-Yong Koo, Ho Kyoon Kwon
• Inventors: KOO, Bon-Yong, KIM, Beom Jun, KWON, Ho Kyoon
• Granted Patent: US 9,024,858 B2
• Time in Patent Office: Days
• US Class Current: 345/87
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2320/0209 Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
• CPC Class Codes: G09G 3/36 using liquid crystals
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

The present invention divides a wire supplying a scan start signal to a gate driver into two wires, so as to avoid overlapping a clock signal line. In this way the clock signal is not delayed by interference, and a gate driving margin may continue uninterrupted, thereby uniformly outputting a gate-on voltage. In particular, if the clock signal line is connected to all stages in the gate driver and the clock signal line overlaps the scan start signal line, unsightly horizontal bands appear on the image and the parallel gate lines generate a very large parasitic capacitance. In contrast, the gate drivers in the present disclosure comprise clock signal lines which do not overlap the scan start signal lines. As benefits, interference resulting in horizontal banding is minimized and the power consumption may be reduced by about 10%.

Claims

1. A display panel comprising:

a display area including a gate line and a data line; and

a gate driver connected to one end of the gate line, including a plurality of normal stages and dummy stages, integrated on a substrate to output a gate voltage,

wherein a supplied scan start signal is transmitted through a first scan start signal wire and a second scan start signal wire,

the first scan start signal wire transmits the scan start signal to a dummy stage of the dummy stages, and

the second scan start signal wire transmits the scan start signal to a first stage of the normal stages.

2. The display panel of claim 1, wherein

the plurality of normal stages and the dummy stages are disposed in one line, and are alternately supplied with a clock signal by wire.

3. The display panel of claim 2, wherein

the first scan start signal wire and the second scan start signal wire are formed on opposite sides of the wire supplying the clock signal.

4. The display panel of claim 3, wherein

the wire and the first scan start signal wire carrying the clock signal are formed on the same layer as the gate line, and the second scan start signal wire is formed on the same layer as the gate line and the data line, thereby having a dual-layered structure.

5. The display panel of claim 4, wherein

the wire supplying the clock signal has a connection to the plurality of normal stages and dummy stages, and the connection is formed on the same layer as the data line.

6. The display panel of claim 4, wherein

the second scan start signal wire is only formed on the same layer as the gate line at a portion connected to the first stage.

7. The display panel of claim 3, wherein

a flexible printed circuit is attached to one side of the display panel and a printed circuit board (PCB) is attached to the other end of the flexible printed circuit, and

one scan start signal is output in a driving voltage generating circuit of the printed circuit board (PCB), and the flexible printed circuit divides one scan start signal into two wires and transmits them separately to the display panel.

8. The display panel of claim 3, wherein

each normal stage receives the clock signal, a first low voltage and a second low voltage lower than the first low voltage, at least one transmission signal from among previous stages, and at least two transmission signals from among following stages to output a gate voltage having the first low voltage as a gate-off voltage.

9. The display panel of claim 8, wherein

the gate voltage when the transmission signal is low is the second low voltage.

10. The display panel of claim 8, wherein

the normal stage comprises an input section, a pull-up driver, a pull-down driver, an output unit, and a transmission signal generator.

11. The display panel of claim 8, wherein

the dummy stage comprises a first dummy stage and a second dummy stage.

12. The display panel of claim 11, wherein

the first dummy stage receives the clock signal, the first low voltage and the second low voltage lower than the first low voltage, at least one transmission signal from among the previous stages, at least one transmission signal from among the following stages, and the scan start signal,

to output a dummy gate voltage having the first low voltage as the gate-off voltage.

13. The display panel of claim 12, wherein

the second dummy stage receives the clock signal, the first low voltage and the second low voltage lower than the first low voltage, the transmission signal of the first dummy stage, and the scan start signal,

to output a dummy gate voltage having the first low voltage as the gate-off voltage.

14. The display panel of claim 11, wherein

the normal stage comprises a seventeenth transistor, wherein

a control terminal of the seventeenth transistor is connected to a second input terminal of the normal stage;

an input terminal of the seventeenth transistor is connected to a transmission signal output terminal of the normal stage;

and an output terminal of the seventeenth transistor is connected to a second voltage input terminal of the normal stage; and

wherein

the first dummy stage and the second dummy stage also each include a seventeenth transistor,

the seventeenth transistors of each of the first and second dummy stages comprising a transistor control terminal connected to a dummy stage first input terminal, a transistor input terminal connected to a dummy stage transmission signal output terminal, and a transistor output terminal connected to a dummy stage second voltage input terminal.

15. The display panel of claim 11, wherein

the normal stage comprises a diode-connected sixteenth transistor, and

the first dummy stage and the second dummy stage do not form an additional element at a position corresponding to the sixteenth transistor.

16. The display panel of claim 11, wherein

the normal stage and the first dummy stage each comprise a sixth transistor, wherein

a control terminal of the sixth transistor is connected to a third input terminal of a stage,

an output terminal of the sixth transistor is connected to a second voltage input terminal of a stage,

and an input terminal of the sixth transistor is connected to a Q node of a stage, and

the second dummy stage does not form an additional element at a position corresponding to the sixth transistor and does not have a third input terminal.

17. The display panel of claim 11, wherein

the second dummy stage further comprises an eighteenth transistor, wherein

the control terminal of the eighteenth transistor is connected to a second input terminal of the second dummy stage,

an input terminal of the eighteenth transistor is connected to a transmission signal output terminal of the second dummy stage,

and an output terminal of the eighteenth transistor is connected to a second voltage input terminal.

18. The display panel of claim 17, wherein

the second dummy stage further comprises a nineteenth transistor, wherein

the control terminal of the nineteenth transistor is connected to a transmission signal output terminal of the second dummy stage,

an input terminal of the nineteenth transistor is connected to a Q node of the second dummy stage,

and an output terminal of the nineteenth transistor is connected to the second voltage input terminal of the second dummy stage.