SOLID-STATE IMAGING DEVICE, AND METHOD FOR DRIVING THE SAME

• US 20130107094A1
• Filed: 12/20/2012
• Published: 05/02/2013
• Est. Priority Date: 07/09/2010
• Status: Active Grant

• Current Assignee: Panasonic Intellectual Property Management Co., Ltd. (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: YAMAMOTO, Takahiro, YARINO, Makoto, MATSUNAGA, Yoshiyuki
• Granted Patent: US 8,994,864 B2
• Time in Patent Office: Days
• US Class Current: 348/302
• CPC Class Codes: H01L 27/1461 characterised by the photosensitive area
• CPC Class Codes: H01L 27/14692 Thin film technologies, e.g. amorphous, poly, micro- or nanocrystalline silicon
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array

Abstract

A solid-state imaging device according to the present invention includes: a semiconductor substrate; a plurality of pixels disposed on the semiconductor substrate in rows and columns; a column signal line formed for each of the columns; an inverting amplifier connected to the column signal line; and a feedback line, provided for each of the columns, to feed back output signal of the inverting amplifier to pixels in a corresponding column, wherein the amplifying transistor includes a gate connected to the pixel electrode and outputs signal voltage corresponding to the pixel electrode to a column signal line via the selection transistor, and one of a source and a drain of the reset transistor is connected to the pixel electrode and the other is connected to a corresponding feedback line.

Claims

1. A solid-state imaging device comprising:

a semiconductor substrate;

a plurality of pixels disposed on the semiconductor substrate in rows and columns;

a column signal line formed for each of the columns;

an inverting amplifier connected to each of the column signal lines; and

a feedback line provided, for each of the columns, to feed back an output signal of the inverting amplifier to the pixels in the column,

wherein each of the pixels includes

a reset transistor, a selection transistor, an amplifying transistor, and a photoelectric conversion unit,

the photoelectric conversion unit includes;

a photoelectric conversion film which performs photoelectric conversion;

a pixel electrode formed on a surface of the photoelectric conversion film on a side of the semiconductor substrate; and

a transparent electrode formed on a surface of the photoelectric conversion film on an opposite side of the pixel electrode,

wherein the amplifying transistor has a gate connected to the pixel electrode and outputs signal voltage corresponding to potential of the pixel electrode to the column signal line via the selection transistor, and

the reset transistor has one of a source and a drain connected to the pixel electrode and the other of the source and the drain connected to a corresponding feedback line.

2. The solid-state imaging device according to claim 1,

wherein a row selection signal is applied to a gate of the selection transistor,

a row reset signal is applied to a gate of the reset transistor, and

the row reset signal is validated after a certain period of time following validation of the row selection signal, and is valid for a period within a period of time in which the row selection signal is valid.

3. The solid-state imaging device according to claim 2, further comprising

a waveform adjusting unit configured to adjust a waveform of the row reset signal to be applied to the gate of the reset transistor,

wherein the waveform adjusting unit is configured to adjust the waveform of a reset pulse of the reset signal to have a slope at a trailing edge, and to provide the gate of the reset transistor with the reset signal including the adjusted reset pulse.

4. The solid-state imaging device according to claim 3,

wherein the solid-state imaging device is capable of switching between imaging at a first frame rate and imaging at a second frame rate that is higher than the first frame rate, and

the waveform adjusting unit is configured to adjust the reset pulse to have a slope of the trailing edge so that transition time for the imaging at the first frame rate is longer than transition time for the imaging at the second frame rate, the transition time being required for the trailing edge of the reset pulse to fall or rise.

5. The solid-state imaging device according to claim 3,

wherein the waveform adjusting unit is a filter circuit which is inserted into a reset control line connected to the gate of the reset transistor.

6. The solid-state imaging device according to claim 5,

wherein the waveform adjusting unit is configured to adjust the slope of the trailing edge of the reset pulse by changing a circuit constant of the filter circuit.

7. The solid-state imaging device according to claim 3,

wherein the waveform adjusting unit includes a digital-to-analog converter which outputs, as the row reset signal, an analog signal having a slope at the trailing edge of the reset pulse.

8. The solid-state imaging device according to claim 2, further comprising

a waveform adjusting unit configured to adjust a waveform of the row reset signal to be applied to the gate of the reset transistor,

wherein the waveform adjusting unit is configured to adjust a frequency band of a trailing edge of the reset pulse included in the row reset signal.

9. The solid-state imaging device according to claim 3,

wherein the waveform adjusting unit is further configured to receive a row reset signal before waveform adjustment having an amplitude corresponding to a power source voltage, and to adjust the waveform to reduce the amplitude of the row reset signal.

10. The solid-state imaging device according to claim 3,

wherein the amplitude of the row reset signal to be applied to the gate of the reset transistor is smaller than a maximum voltage to be applied to the drain of the amplifying transistor.

11. The solid-state imaging device according to claim 3,

wherein the amplitude of the row reset signal to be applied to the gate of the reset transistor is smaller than a maximum voltage to be applied to the gate of the selection transistor.

12. The solid-state imaging device according to claim 3,

wherein the amplitude of the row reset signal to be applied to the gate of the reset transistor is smaller than a power source voltage to be applied to the inverting amplifier.

13. The solid-state imaging device according to claim 3,

wherein the amplitude of the row reset signal to be applied to the gate of the reset transistor is smaller than a maximum voltage to be applied to the transparent electrode.

14. The solid-state imaging device according to claim 3,

wherein the amplitude of the row reset signal to be applied to the gate of the reset transistor is smaller than:

(a) a maximum voltage to be applied to the drain of the amplifying transistor;

(b) a maximum voltage to be applied to the gate of the selection transistor;

(c) a power source voltage to be applied to the inverting amplifier; and

(d) a maximum voltage to be applied to the transparent electrode.

15. A solid-state imaging device comprising:

a plurality of pixels disposed on a semiconductor substrate in rows and columns;

a row scanning unit configured to generate a row reset signal; and

a waveform adjusting unit configured to adjust a waveform of the row reset signal to be applied to a gate of the reset transistor,

wherein each of the pixels includes

a reset transistor, a selection transistor, an amplifying transistor, and a photoelectric conversion unit,

the photoelectric conversion unit includes;

a photoelectric conversion film which performs photoelectric conversion;

a pixel electrode formed on a surface of the photoelectric conversion film on a side of the semiconductor substrate; and

a transparent electrode formed on a surface of the photoelectric conversion film on an opposite side of the pixel electrode,

wherein the amplifying transistor has a gate connected to the pixel electrode and outputs signal voltage corresponding to potential of the pixel electrode to a column signal line via the selection transistor, and

the waveform adjusting unit is configured to adjust the waveform of a reset pulse of the reset signal to have a slope at a trailing edge, and to provide the adjusted row reset signal to the gate of the reset transistor.

16. A method for driving a solid-state imaging device,

wherein the solid-state imaging device includes:

a semiconductor substrate;

a plurality of pixels disposed on the semiconductor substrate in rows and columns;

a column signal line formed for each of the columns;

an inverting amplifier connected to each of the column signal lines; and

a feedback line provided, for each of the columns, to feed back an output signal of the inverting amplifier to the pixels in the column,

wherein each of the pixels includes

a reset transistor, a selection transistor, an amplifying transistor, and a photoelectric conversion unit,

the photoelectric conversion unit includes;

a photoelectric conversion film which performs photoelectric conversion;

a pixel electrode formed on a surface of the photoelectric conversion film on a side of the semiconductor substrate; and

a transparent electrode formed on a surface of the photoelectric conversion film on an opposite side of the pixel electrode,

wherein the amplifying transistor has a gate connected to the pixel electrode and outputs signal voltage corresponding to potential of the pixel electrode to the column signal line via the selection transistor, and

the reset transistor has one of a source and a drain connected to the pixel electrode and the other of the source and the drain connected to a corresponding feedback line,

the method for driving the solid-state imaging device comprising;

outputting an output signal of the amplifying transistor to a column signal line by validating a row selection signal in a gate of the selection transistor; and

feeding back an output of the inverting amplifier via the reset transistor to the pixel electrode by validating the row reset signal after a certain period of time following validation of the row selection signal.