PERFORMING FORMING PROCESSES ON RESISTIVE MEMORY

• US 20130107605A1
• Filed: 11/01/2011
• Published: 05/02/2013
• Est. Priority Date: 11/01/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Chen, Xiaonan
• Granted Patent: US 8,730,708 B2
• Time in Patent Office: Days
• US Class Current: 365/148
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0073 Write using bi-directional cell biasing
• CPC Class Codes: G11C 2013/0083 Write to perform initialising, forming process, electro forming or conditioning
• CPC Class Codes: G11C 2013/0092 Write characterized by the shape, e.g. form, length, amplitude of the write pulse
• CPC Class Codes: Y10T 29/49002 Electrical device making

Abstract

The present disclosure includes apparatuses and methods for performing forming processes on resistive memory. A number of embodiments include applying a formation signal to the storage element of a resistive memory cell, wherein the formation signal includes a first portion having a first polarity and a first amplitude, a second portion having a second polarity and a second amplitude, wherein the second polarity is opposite the first polarity and the second amplitude is smaller than the first amplitude, and a third portion having the first polarity and a third amplitude that is smaller than the first amplitude.

Claims

1. A method of performing a forming process on a storage element of a resistive memory cell, the method comprising:

applying a formation signal to the storage element, wherein the formation signal includes;

a first portion having a first polarity and a first amplitude;

a second portion having a second polarity and a second amplitude, wherein the second polarity is opposite the first polarity and the second amplitude is smaller than the first amplitude; and

a third portion having the first polarity and a third amplitude that is smaller than the first amplitude.

2. The method of claim 1, wherein the method includes applying the formation signal to the storage element as part of a forming process performed on the storage element.

3. The method of claim 1, wherein the formation signal is an initialization signal.

4. The method of claim 1, wherein applying the formation signal to the storage element forms a filament in the resistive memory cell.

5. The method of claim 1, wherein the first polarity is positive.

6. The method of claim 1, wherein the third amplitude is approximately equal to the second amplitude.

7. The method of claim 1, wherein:

the first portion has a first duration;

the second portion has a second duration that is shorter than the first duration; and

the third portion has a third duration that is shorter than the first duration.

8. The method of claim 7, wherein the third duration is approximately equal to the second duration.

9. A method of performing a forming process on a storage element of a resistive memory cell, the method comprising:

applying a first pulse having a first polarity and a first amplitude to the storage element in order to induce formation of an initial filament in the resistive memory cell;

applying a second pulse having a second polarity and a second amplitude to the storage element, wherein the second polarity is opposite the first polarity and the second amplitude is smaller than the first amplitude; and

applying a third pulse having the first polarity and a third amplitude that is smaller than the first amplitude to the storage element.

10. The method of claim 9, wherein the method includes applying the second pulse to the storage element in order to rupture a resistive portion of the initial filament.

11. The method of claim 10, wherein the method includes applying the third pulse to the storage element in order to form a complete filament.

12. The method of claim 9, wherein the method includes:

applying the second pulse to the storage element after applying the first pulse to the storage element; and

applying the third pulse to the storage element after applying the second pulse to the storage element.

13. The method of claim 9, wherein the resistive memory cell is a virgin resistive memory cell.

14. The method of claim 9, wherein the method includes applying a compliance current to the storage element while applying the first and third pulses to the storage element.

15. A method of performing a forming process on a storage element of a resistive memory cell, comprising:

applying a first set pulse having a first amplitude to the storage element;

applying a reset pulse having a second amplitude that is smaller than the first amplitude to the storage element; and

applying a second set pulse having a third amplitude that is smaller than the first amplitude to the storage element.

16. The method of claim 15, wherein the first set pulse is a positive pulse.

17. The method of claim 15, wherein the reset pulse is a negative pulse.

18. The method of claim 15, wherein the second set pulse is a positive pulse.

19. A memory apparatus, comprising:

an array of resistive memory cells; and

a controller coupled to the array and configured to perform a forming process on a storage element of a number of resistive memory cells of the array via a formation signal that includes;

a first portion having a first polarity and a first amplitude;

a second portion having a second polarity and a second amplitude, wherein the second polarity is opposite the first polarity and the second amplitude is smaller than the first amplitude; and

a third portion having the first polarity and a third amplitude that is smaller than the first amplitude.

20. The memory apparatus of claim 19, wherein the formation signal has a duration of approximately 3.0 to 5.0 microseconds.

21. The memory apparatus of claim 19, wherein the controller is configured to apply a programming signal to the number of resistive memory cells after applying the formation signal to the storage element, wherein the programming signal includes at least one of a set pulse and a reset pulse.

22. The memory apparatus of claim 19, wherein the array is a resistive random access memory array.

23. A memory apparatus, comprising:

an array of resistive memory cells; and

a controller coupled to the array and configured to;

apply a first set pulse having a first amplitude to a storage element of a number of resistive memory cells of the array;

apply a reset pulse having a second amplitude that is smaller than the first amplitude to the storage element; and

apply a second set pulse having a third amplitude that is smaller than the first amplitude to the storage element;

wherein the first set, reset, and second set pulses are applied to the storage element in a forming process.

24. The memory apparatus of claim 23, wherein the first and second set pulses have a positive polarity.

25. The memory apparatus of claim 23, wherein the controller is configured to apply the first set, reset, and second set pulses to the storage element as a combined pulse.

26. The memory apparatus of claim 23, wherein the storage element includes a metal oxide material.

27. The memory apparatus of claim 23, wherein the forming process produces a filament including a number of oxygen vacancies.

28. The memory apparatus of claim 23, wherein the forming process produces a filament including a number of metal precipitates.

29. A method of performing a forming process on a storage element of a resistive memory cell, the method comprising:

applying a formation signal to the storage element, wherein;

a first portion of the formation signal induces formation of an initial filament including a resistive portion;

a second portion of the formation signal ruptures the resistive portion of the initial filament; and

a third portion of the formation signal forms a complete filament.

30. The method of claim 29, wherein the initial filament is an incomplete filament.

31. The method of claim 29, wherein the initial filament includes only a portion of a complete filament.

32. The method of claim 29, wherein:

the second portion of the formation signal forms a gap in the initial filament where the resistive portion was previously located; and

the third portion of the formation signal completes the gap in the initial filament to form the complete filament.

33. The method of claim 29, wherein the first, second, and third portions of the formation signal are first, second, and third pulses, respectively.

34. An apparatus, comprising:

an array of resistive memory cells; and

a controller coupled to the array and configured to apply a formation signal to a storage element of a number of resistive memory cells of the array, wherein;

a first portion of the formation signal induces formation of an initial filament including a resistive portion;

a second portion of the formation signal ruptures the resistive portion of the initial filament; and

a third portion of the formation signal forms a complete filament.