MEMORY CELL SENSING

• US 20130107623A1
• Filed: 11/01/2011
• Published: 05/02/2013
• Est. Priority Date: 11/01/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Park, Jae-Kwan, Kavalipurapu, Kalyan C.
• Granted Patent: US 8,891,297 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells

Abstract

This disclosure concerns memory cell sensing. One or more methods include determining a data state of a first cell coupled to a first data line in response to a request to sense a data state of a second cell coupled to a second data line, applying a reference voltage to the first data line, floating the second data line while adjusting a voltage of the first data line to an adjusted voltage associated with the determined data state of the first cell, determining an effect on the second data line due, at least in part, to the adjusting the voltage of the first data line, and sensing the data state of the second cell by applying a particular sensing voltage to a selected access line to which the first cell and the second cell are coupled, the particular sensing voltage based on the determined effect on the second data line.

Claims

1. A method for operating a memory, comprising:

determining a data state of a first memory cell coupled to a first data line in response to a request to sense a data state of a second memory cell coupled to a second data line adjacent the first data line;

applying a reference voltage to the first data line;

floating the second data line while adjusting a voltage of the first data line from the reference voltage to an adjusted voltage associated with the determined data state of the first memory cell;

determining an effect on the second data line due, at least in part, to the adjusting the voltage of the first data line; and

sensing the data state of the second memory cell by applying a particular sensing voltage to a selected access line to which the first memory cell and the second memory cell are coupled, the particular sensing voltage based, at least partially, on the determined effect on the second data line.

2. The method of claim 1, wherein applying a reference voltage to the first data line further includes applying the reference voltage to the second data line.

3. The method of claim 1, further comprising, while floating the first data line, determining the effect on the second data line due, at least in part, to the adjusting the voltage of the first data line.

4. The method of claim 1, wherein determining the effect on the second data line includes sensing whether a voltage on the second data line is different than the reference voltage.

5. The method of claim 1, wherein determining the effect on the second data line includes sensing whether a voltage on the second data line is above or below at least a first voltage threshold level.

6. The method of claim 1, wherein the method includes programming the first and the second memory cell in accordance with a shielded data line technique prior to receiving the request to sense the data state of the second memory cell.

7. The method of claim 1, wherein floating the second data line while adjusting a voltage of the first data line to the adjusted voltage associated with the determined data state of the first memory cell changes a voltage of the second data line due, at least partially, to capacitive coupling between the first and the second data line.

8. The method of claim 1, including:

determining a data state of a third memory cell coupled to a third data line in response to the request to sense the data state of the second memory cell, the third data line is adjacent to the second data line;

while the second data line is floating, adjusting a voltage of the third data line from the reference voltage to an adjusted voltage associated with the data state of the third memory cell;

while floating the first data line and the third data line, determining an effect on the second data line due, at least in part, to the adjusting the voltage of the first data line, the adjusting the voltage of the third data line, and a capacitive coupling between at least the first and the second data line and between at least the second and the third data line; and

wherein sensing the data state of the second memory cell by applying the particular sensing voltage to the selected access line includes applying a particular sensing voltage to the selected access line that is based, at least partially, on the determined effect on the second data line due, at least in part, to the capacitive coupling between at least the first and the second data line and between at least the second and the third data line.

9. The method of claim 1, wherein the first and the second memory cell are multilevel memory cells (MLCs).

10. A method for operating a memory, comprising:

determining data stored by a first memory cell coupled to a first data line and a second memory cell coupled to a third data line in response to a request to sense data stored by a target memory cell coupled to a second data line adjacent the first data line and the third data line; and

sensing the data stored by the target memory cell using a sensing voltage applied to a selected access line to which the first memory cell, the second memory cell, and the target memory cell are coupled, the sensing voltage based, at least partially, on the data stored by the first memory cell and the second memory cell and determined by;

floating the second data line while adjusting voltages of the first data line and the third data line to adjusted voltages associated with the data stored by the respective first memory cell and second memory cell; and

determining an effect on the second data line due, at least in part, to the adjusted voltages and a capacitive coupling between at least the first and the second data line and between the second and the third data line.

11. The method of claim 10, further comprising floating the first and third data lines while determining the effect on the second data line due, at least in part, to the adjusted voltages and the capacitive coupling between at least the first and the second data line and between the second and the third data line.

12. A method for operating a memory, comprising:

determining data states of a first subset of memory cells in response to a request to sense data states of a second subset of memory cells;

floating the data lines to which the second subset of memory cells are coupled while adjusting voltages of the data lines to which the first subset of memory cells are coupled from a reference voltage to adjusted voltages associated with the determined data state of each of the respective memory cells of the first subset;

while floating the data lines coupled to the first subset of memory cells, determining an effect on the data lines to which the second subset of memory cells are coupled due, at least in part, to the adjusting the voltages of the data lines to which the first subset of memory cells are coupled; and

sensing the data states of a number of the second subset of memory cells by applying a particular sensing voltage to a selected access line to which the first subset and the second subset of memory cells are coupled, the particular sensing voltage based, at least partially, on the determined effect on the data lines to which the number of the second subset of memory cells are coupled.

13. The method of claim 12, wherein the number of the second subset of memory cells comprises a first number of the second subset, and wherein the method includes sensing the data states of a second number of the second subset of memory cells by applying a different particular sensing voltage to the selected access line, the different particular sensing voltage based, at least partially, on the determined effect on the data lines to which the second number of the second subset of memory cells are coupled.

14. The method of claim 13, wherein the method includes sensing the data states of a third number of the second subset of memory cells by applying an additional different particular sensing voltage to the selected access line, the additional different particular sensing voltage based, at least partially, on the determined effect on the data lines to which the third number of the second subset of memory cells are coupled.

15. The method of claim 12, wherein determining the effect on the data lines to which the second subset of memory cells are coupled due, at least in part, to the adjusting the voltage of the data lines to which the first subset of memory cells are coupled includes determining whether at least one of the memory cells coupled to data lines directly adjacent the data lines to which the second subset of memory cells are coupled are programmed to a particular data state.

16. The method of claim 15, wherein the particular data state is an erased data state.

17. The method of claim 15, wherein the particular data state is a non-erased data state.

18. A memory apparatus, comprising:

an array of memory cells including a first subset of data lines and a second subset of data lines, wherein each data line of the first subset is adjacent to, and shares a common data line control component with, a data line of the second subset; and

a controller coupled to the array and configured to control a method that includes;

determining data states of memory cells coupled to a selected access line and to the first subset in response to a request to sense data states of memory cells coupled to the selected access line and to the second subset;

floating the second subset while adjusting voltages on data lines of the first subset to adjusted voltages associated with respective determined data states of the memory cells coupled to the first subset;

determining an effect on the data lines of the second subset due, at least in part, to the adjusting the voltages on the data lines of the first subset to the adjusted voltages;

responsive to the determined effect on the data lines of the second subset, determining a sensing voltage to be applied to the selected access line to sense the data states of the memory cells coupled to the selected access line and to the data lines of the second subset.

19. The apparatus of claim 18, wherein the controller is configured to control adjusting voltages on data lines of the first subset from a reference voltage applied to the first and to the second subset to the adjusted voltages.

20. The apparatus of claim 18, wherein the adjusted voltages associated with respective determined data states of the memory cells coupled to the first subset corresponds to either an erased data state or to a non-erased data state of the memory cells.

21. The apparatus of claim 18, wherein the controller is configured to control determining the effect on the respective data lines of the second subset by controlling performance of a number of sensing operations on the respective data lines of the second subset while floating the data lines of the first subset.

22. The apparatus of claim 21, wherein the controller is configured to control performance of the number of sensing operations by controlling performance of a first sensing operation to determine if a voltage on the respective data lines of the second subset has changed from the reference voltage to at least a first voltage threshold level.

23. The apparatus of claim 22, wherein the controller is configured to control performance of the number of sensing operations by controlling performance of a second sensing operation to determine if the voltage on the respective data lines of the second subset has changed from the reference voltage to at least a second voltage threshold level.

24. The apparatus of claim 22, wherein those data lines of the second subset determined to have a voltage less than the first voltage threshold level responsive to the first sensing operation conduct current responsive to the first sensing operation, and wherein the controller is configured to control performance of a clean up operation to adjust a voltage on those data lines of the second subset determined to have a voltage less than the first voltage threshold level subsequent to the first sensing operation.

25. The apparatus of claim 22, wherein those data lines of the second subset determined to have a voltage greater than the first voltage threshold level responsive to the first sensing operation conduct current responsive to the first sensing operation, and wherein the controller is configured to control performance of a clean up operation to adjust a voltage on those data lines of the second subset determined to have a voltage greater than the first voltage threshold level subsequent to the first sensing operation.

26. The apparatus of claim 23, wherein the controller is configured to control performing the second sensing operation on only those data lines of the second subset determined to have a voltage less than the first voltage threshold level.

27. The apparatus of claim 23, wherein the controller is configured to control performing the second sensing operation on only those data lines of the second subset determined to have a voltage greater than the first voltage threshold level.

28. The apparatus of claim 23, wherein the controller is configured to control:

applying a first sensing voltage to the selected access line to sense the data states of those memory cells coupled to the selected access line and to respective data lines of the second subset having a voltage determined not to have changed from the reference voltage to at least the first voltage threshold level responsive to the first sensing operation;

applying a second sensing voltage to the selected access line to sense the data states of those memory cells coupled to the selected access line and to respective data lines of the second subset having a voltage determined to have changed from the reference voltage to at least the first voltage threshold level responsive to the first sensing operation; and

applying a third sensing voltage to the selected access line to sense the data states of those memory cells coupled to the selected access line and to respective data lines of the second subset having a voltage determined to have changed from the reference voltage to at least the second voltage threshold level responsive to the second sensing operation.

29. The apparatus of claim 28, wherein the first sensing voltage is an unadjusted sensing voltage, the second sensing voltage is a first adjusted sensing voltage, and the third sensing voltage is a second adjusted sensing voltage.

30. The apparatus of claim 18, wherein the controller is configured to control floating the data lines of the first subset while determining the effect on the respective data lines of the second subset, and wherein the effect on the respective data lines of the second subset is due, at least partially, to capacitive coupling associated with adjusting the voltage on the respective data lines of the first subset from the reference voltage to the adjusted voltage.

31. The apparatus of claim 18, wherein the array of memory cells is an array of multilevel memory cells (MLCs).

32. The apparatus of claim 18, wherein the controller is configured to control programming of the memory cells coupled to the selected access line and to the first subset of data lines to final data states, and to control programming the memory cells coupled to the selected access line and to the second subset of data lines to final data states, prior to controlling determining data states of memory cells coupled to the selected access line and to the first subset in response to the request to sense data states of memory cells coupled to the selected access line and to the second subset.

33. A memory apparatus, comprising:

an array of memory cells including a first subset of data lines and a second subset of data lines, wherein each respective data line of the first subset is adjacent to, and shares a common data line control component with, a respective data line of the second subset;

circuitry coupled to the array and configured to;

determine a data state of a memory cell coupled to a selected access line and to a data line of the first subset in response to a request to sense a data state of a target memory cell coupled to the selected access line and to a data line of the second subset;

determine a programmed status of the memory cell coupled to the data line of the first subset by performing a sensing operation on the data line of the second subset; and

determine a particular sensing voltage to be applied to the selected access line to sense the data state of the target cell based, at least partially, on the determined programmed status of the memory cell coupled to the data line of the first subset.

34. The memory apparatus of claim 33, wherein the memory cell coupled to the data line of the first subset comprises a first memory cell coupled to a first data line of the first subset, and wherein the circuitry coupled to the array is configured to determine a data state of a second memory cell coupled to the selected access line and to a second data line of the first subset in response to the request to sense the data state of the target memory cell.

35. The memory apparatus of claim 34, wherein the circuitry coupled to the array is configured to:

determine a programmed status of the second memory cell by performing the sensing operation on the data line of the second subset; and

determine the particular sensing voltage to be applied to the selected access line to sense the data state of the target cell based, at least partially, on the determined programmed status of the first and the second memory cell.

36. The memory apparatus of claim 35, wherein the circuitry coupled to the array is configured to float the first data line and the second data line while performing the sensing operation on the data line of the second subset.

37. The memory apparatus of claim 33, wherein the memory cell coupled to the data line of the first subset comprises a first memory cell coupled to a first data line of the first subset, and wherein a second data line of the first subset shares a data line control component with the data line of the second subset, and wherein the common data line control component is configured to hold the second data line of the first subset at a reference voltage while performing the sensing operation on the data line of the second subset.