CLOCK AND DATA RECOVERY FOR NFC TRANSCEIVERS

• US 20130107913A1
• Filed: 10/26/2011
• Published: 05/02/2013
• Est. Priority Date: 10/26/2011
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Savoj, Jafar
• Granted Patent: US 9,124,413 B2
• Time in Patent Office: Days
• US Class Current: 375/219
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H04B 5/00 Near-field transmission systems, e.g. inductive or capacitive transmission systems
• CPC Class Codes: H04B 5/48 Transceivers
• CPC Class Codes: H04L 27/02 Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation H04L27/32 takes precedence
• CPC Class Codes: H04L 27/06 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence
• CPC Class Codes: H04L 7/10 Arrangements for initial synchronisation

Abstract

Exemplary embodiments are directed to data and clock recovery in NFC transceivers. A transceiver may include a phase-locked loop configured to recover a clock from a received input signal in a first mode and enable for oversampling of an output signal in a second, different mode.

Claims

1. A transceiver comprising a phase-locked loop configured to recover a clock from a received input signal in a first mode and enable for oversampling of an output signal in a second, different mode.

2. The transceiver of claim 1, the phase-locked loop comprising a first voltage controlled oscillator for use in the first mode and a second voltage controlled oscillator for use in the second mode.

3. The transceiver of claim 1, the phase-locked loop comprising a phase-frequency detector including an amplitude-shift keying detection circuit configured to detect an amplitude-shift keying mode.

4. The transceiver of claim 3, the amplitude-shift keying detection circuit comprising a plurality of flip-flop circuits.

5. The transceiver of claim 1, the phase-locked loop comprising a plurality of multiplexers for selecting one of a first path and a second path.

6. The transceiver of claim 5, the first path comprising a first frequency and a first power level and the second path comprising a second frequency greater than the first frequency and a second power level greater than the first power level.

7. The transceiver of claim 1, the phase-locked loop comprising:

a first circuit path including a first voltage controlled oscillator, the first circuit path for oversampling of the output signal; and

a second circuit path including a first voltage controlled oscillator having a frequency lower than a frequency of the first voltage controlled oscillator, the second circuit path for recovering the clock from the received input signal.

8. A phase-locked loop, comprising:

a frequency-phase detector; and

an amplitude-shift keying detection circuit coupled to the frequency-phase detector and configured to detect an amplitude-shift keying mode.

9. The phase-locked loop of claim 8, the amplitude-shift keying detection circuit comprising a plurality of flip-flop circuits.

10. The phase-locked loop of claim 9, each flip-flop circuit of the plurality of flip-flops configured to sample an input signal at an edge of an associated voltage controlled oscillator signal.

11. The phase-locked loop of claim 9, the amplitude-shift keying detection circuit further comprising a XOR gate coupled to an output of each flip-flop of the plurality of flip-flops.

12. The phase-locked loop of claim 8, the amplitude-shift keying detection circuit configured to convey a signal to the frequency-phase detector to reset the frequency-phase detector upon detection of the amplitude-shift keying mode.

13. The phase-locked loop of claim 8, an output of the amplitude-shift keying detection circuit coupled to an NAND gate of the frequency-phase detector.

14. A method, comprising:

recovering a clock from a received input signal with a phase-locked loop in a first near-field communication (NFC) mode; and

oversampling of an output signal with the phase-locked loop in a second, different NFC mode.

15. The method of claim 14, further comprising detecting an amplitude-shift keying mode while in the first NFC mode.

16. The method of claim 14, the recovering comprising utilizing a first circuit path of the phase-locked loop and the oversampling comprising utilizing a second, different circuit path of the phase-locked loop.

17. The method of claim 14, the recovering comprising recovering the clock from the received input signal in a tag mode

18. The method of claim 14, the oversampling comprising oversampling the output signal in an initiator mode.

19. A method, comprising:

receiving an input signal at a phase-frequency detector in a tag mode; and

detecting an amplitude-shift keying mode while receiving the input signal in the tag mode.

20. The method of claim 19, further comprising resetting the phase-frequency detector upon detecting the amplitude-shift keying mode.

21. The method of claim 19, the detecting comprising detecting a consecutive number of zeros in the input signal.

22. The method of claim 19, the detecting comprising sampling the input signal with a plurality of flip-flop circuits.

23. The method of claim 19, the sampling comprising sampling the input signal at each of a rising edge and a falling edge of an output of an associated voltage controlled oscillator.

24. A device, comprising:

means for recovering a clock from a received input signal with a phase-locked loop in a first NFC mode; and

means for oversampling of an output signal with the phase-locked loop in a second, different NFC mode.

25. A device, comprising:

means for receiving an input signal at a phase-frequency detector in a tag mode; and

means for detecting an amplitude-shift keying mode while receiving the input signal in the tag mode.