METHOD OF FORMING SEMICONDUCTOR DEVICES USING SMT

• US 20130109186A1
• Filed: 10/26/2012
• Published: 05/02/2013
• Est. Priority Date: 11/02/2011
• Status: Abandoned Application

• Current Assignee: Shanghai Huali Microelectronics Corporation
• Original Assignee: Shanghai Huali Microelectronics Corporation
• Inventors: ZHANG, Wenguang, XU, Qiang, Zheng, Chunsheng, Chen, Yuwen, Xu, Lingzhi
• Application Number:
  US13/662,277
• Publication Number:
  US 20130109186A1
• Time in Patent Office: Days
• US Class Current: 438/703
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7847 using a memorization technique, e.g. re-crystallization under strain, bonding on a substrate having a thermal expansion coefficient different from the one of the region

Abstract

The present invention provides a method of forming semiconductor devices using SMT. The method comprises providing a substrate; depositing an SiO₂ buffer film and a low tensile stress SiN film on the substrate; applying photoresist over the low tensile stress SiN film and exposing the low tensile stress SiN film on the NMOS region through photoresist exposure; applying UV radiation to the exposed low tensile stress SiN film; removing some hydrogen in the low tensile stress SiN film on the NMOS region and removing photoresist over the PMOS region; performing a rapid thermal annealing process to induce tensile stress in the NMOS channel region; and removing the SiN film and the SiO₂ buffer film. According to the method of forming semiconductor devices using SMT of the present invention, the conventional SMT is greatly simplified.

Claims

1. A method of forming semiconductor devices using SMT comprising:

Step 1;

providing a substrate including NMOS region and PMOS region;

Step 2;

depositing an SiO₂ buffer film and a low tensile stress SiN film on the substrate sequentially followed by applying photoresist over the low tensile stress SiN film;

Step 3;

exposing the low tensile stress SiN film on the NMOS region through photoresist exposure and applying UV radiation to the exposed low tensile stress SiN film;

removing some hydrogen element in the low tensile stress SiN film on the NMOS region and removing photoresist over the PMOS region;

Step 4;

performing a rapid thermal annealing process to induce tensile stress in the NMOS channel region;

Step 5;

removing the SiN film and the SiO₂ buffer film.

2. The method according to claim 1, wherein, the silicon oxide buffer film is deposited by PECVD or SACVD.

3. The method according to claim 1, wherein, the SiO₂ buffer film has a thickness of about 50 Å

˜

200 Å

.

4. The method according to claim 1, wherein, the stress of the low tensile stress SiN film has a magnitude in the range from about 200 MPa to 400 MPa.

5. The method according to claim 4, wherein, the low tensile stress SiN film has a thickness of about 200 Å

˜

800 Å

.

6. The method according to claim 5, wherein, the stress of the low tensile stress SiN film has a magnitude in the range from about 1000 MPa to 1800 MPa after being exposed and applied UV radiation in step 3.

7. The method according to claim 6, the UV radiation is applied for about 1 minute to 10 minutes.