TEST INSTRUMENT HAVING A CONFIGURABLE INTERFACE

• US 20130110446A1
• Filed: 10/28/2011
• Published: 05/02/2013
• Est. Priority Date: 10/28/2011
• Status: Active Grant

• Current Assignee: Teradyne Incorporated
• Original Assignee: Teradyne Incorporated
• Inventors: Bourassa, Stephen J., McGoldrick, Michael Francis, Kaushansky, David, Fluet, Michael Thomas
• Granted Patent: US 9,470,759 B2
• Time in Patent Office: Days
• US Class Current: 702/122
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/31704 Design for test; Design verification concerning scan tests G01R31/318583; computer-aided design G06F30/00
• CPC Class Codes: G01R 31/31908 Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
• CPC Class Codes: G01R 31/31926 Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing

Abstract

In general, a test instrument includes a processing system programmed to control operation of the test instrument, including communication with a control system, and programmed to run one or more test programs to test a device interfaced to the test instrument, the processing system including multiple processing devices, and a configurable interface, through which communications are exchanged with the device interfaced to the test instrument, the configurable interface including physical ports, to which different configurations are assignable.

Claims

1. A test instrument comprising:

a processing system programmed to control operation of the test instrument, including communication with a control system, and programmed to run one or more test programs to test a device interfaced to the test instrument, the processing system comprising multiple processing devices; and

a configurable interface, through which communications are exchanged with the device interfaced to the test instrument, the configurable interface comprising physical ports, to which different configurations are assignable.

2. The test instrument of claim 1, wherein the configurable interface comprises programmable logic, the logic being programmable through application of a load to the logic, the load providing functionality that enables the physical ports to assume the different configurations.

3. The test instrument of claim 2, wherein the programmable logic comprises a field programmable gate array (FPGA);

and

wherein the load is a single load that enables the physical ports to assume the different configurations in response to control inputs.

4. The test instrument of claim 3, wherein the single load further configures the FPGA to perform one or more tests on the device interfaced to the test instrument.

5. The test instrument of claim 1, wherein different configurations are assignable to the physical ports based, at least in part, on which of the multiple processing devices is communicating with the device interfaced to the test instrument.

6. The test instrument of claim 3, wherein the processing system is programmed to provide the control inputs to the FPGA.

7. The test instrument of claim 1, wherein the different configurations relate to functions of the ports, including whether ports operate as inputs or outputs.

8. The test instrument of claim 1, wherein the different configurations relate to widths of the ports.

9. The test instrument of claim 1, wherein the different configurations relate to frequencies of signals transmitted through the ports.

10. The test instrument of claim 1, wherein the different configurations relate to memory depth associated with the ports.

11. The test instrument of claim 1, wherein the processing system comprises:

a first processing sub-system that is programmable to run one or more test programs to test a device interfaced to the test instrument, and that is programmed to control operation of the test instrument; and

a second processing sub-system that is dedicated to device testing, the second processing system comprising multiple processing devices that are programmable to run one or more test programs to test the device.

12. A method comprising:

configuring a processing system to control operation of a test instrument, including communication with a control system, the configuring comprising programming the processing system to run one or more test programs to test a device interfaced to the test instrument, the processing system comprising multiple processing devices; and

providing a configurable interface, through which communications are exchanged with the device interfaced to the test instrument, the configurable interface comprising physical ports, to which different configurations are assignable.

16. The method of claim 12, wherein different configurations are assignable to the physical ports based, at least in part, on which of the multiple processing devices is communicating with the device interfaced to the test instrument.

17. The method of claim 12, wherein the different configurations relate to functions of the ports, including whether ports operate as inputs or outputs.

18. The method of claim 12, wherein the different configurations relate to widths of the ports.

19. The method of claim 12, wherein the different configurations relate to frequencies of signals transmitted through the ports.

20. The method of claim 12, wherein the different configurations relate to memory depth associated with the ports.

13. The method 12, wherein the configurable interface comprises programmable logic, the logic being programmable through application of a load to the logic, the load providing functionality that enables the physical ports to assume the different configurations.

14. The method of claim 13, wherein the programmable logic comprises a field programmable gate array (FPGA);

and

wherein the load is a single load that enables the physical ports to assume the different configurations in response to control inputs.

15. The method of claim 14, wherein the single load further configures the FPGA to perform one or more tests on the device interfaced to the test instrument.