PERIODIC ERROR DETECTION METHOD AND PERIODIC ERROR DETECTION CIRCUIT

• US 20130111276A1
• Filed: 03/13/2012
• Published: 05/02/2013
• Est. Priority Date: 10/28/2011
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: TERAYAMA, Tomoyuki
• Granted Patent: US 8,887,004 B2
• Time in Patent Office: Days
• US Class Current: 714/49
• CPC Class Codes: G06F 11/2236 to test CPU or processors

Abstract

According to one embodiment, a method for detecting a periodic error, the method detecting a periodic processing error of a module controlled by a processor, the processor controlling a periodic processing by booting a peripheral module, the peripheral module outputting periodic triggers with a predetermined interval includes storing a first count value acquired from a counter, a second count value when the processing is started, and a third count value when the processing is completed, calculating a processing time on a basis of the three count values, and comparing the processing time with the predetermined interval to determine whether the periodic processing error occurs.

Claims

1. A method for detecting a periodic error, the method detecting a periodic processing error of a module, execution of processing of the module being controlled by a processor, the processor controlling a periodic processing by booting a peripheral module, the peripheral module outputting periodic triggers with a predetermined interval, comprising:

storing a first count value in a resister included in a capture timer, the first count value being acquired from a counter included in the capture timer by outputting the periodic triggers as a first capture trigger into the capture timer, the counter performing an up-count operation with free-run;

storing a second count value in the resister, the second count value being acquired from the counter by outputting a second capture trigger into the capture timer when the processing of the module is started;

storing a third count value in the resister, the third count value being acquired from the counter by outputting a third capture trigger into the capture timer when the processing of the module is completed;

reading out the first count value, the second count value and the third count value from the resister when the processor is received a complete notice from the module;

calculating a processing time on a basis of the first count value, the second count value and the third count value; and

comparing the processing time with the predetermined interval to determine whether the periodic processing error occurs.

2. The method of claim 1, wherein

in determining whether the periodic processing error occurs, an added value in which a first value and a second value are added is calculated as the processing time, the first value is subtracted the second count value from the first count value and the second value is subtracted the second count value from the third count value, and the added value is compared with the predetermined interval to determine whether the periodic processing error occurs.

3. The method of claim 2, wherein

in determining whether the periodic processing error occurs, the processor executes a periodic error detection program to determine whether the periodic processing error occurs.

4. The method of claim 2, wherein

in determining whether the periodic processing error occurs, a determination circuit connected between the processor and the capture timer determines whether the periodic processing error occurs.

5. The method of claim 1, wherein

the peripheral module is a motor control circuit controlling motor driving and the module is a vector engine executing calculation on vector control of a motor.

6. The method of claim 5, wherein

the motor control circuit performs a first interruption to the processor when the periodic triggers are output, the processor enables the vector engine corresponding to the first interruption, and the vector engine performs a second interruption to the processor when the processing is completed.

7. A periodic error detection circuit, comprising:

a peripheral module outputting periodic triggers with an predetermined interval;

a processor controlling periodic processing by booting the peripheral module;

a module, execution of processing of the module being controlled by the processor;

a capture timer including a counter and a resister, the counter performing an up-count operation with free-run, the resister storing a first count value, the first count value being acquired from the counter by outputting the periodic triggers as a first capture trigger, storing a second count value, the second count value being acquired from the counter by outputting a second capture trigger when the processing of the module is started, and storing a third count value, the third count value being acquired from the counter by outputting a third capture trigger when the processing of the module is completed; and

a determination circuit connected between the processor and the capture timer, the determination circuit calculating a processing time on a basis of the first count value, the second count value and the third count value stored in the resister, comparing the processing time with the predetermined interval to determine whether the periodic processing error occurs, and outputting a determination result into the processor on request from the processor.

8. The periodic error detection circuit of claim 7, wherein

the determination circuit including a first subtracter which subtracts the first count value from the second count value, a second subtracter which subtracts the second count value from the third count value, an adder which adds an input of the first subtracter and an input of the second subtracter, and a comparator which compares an input of the adder with the predetermined interval to determine whether the periodic processing error occurs.

9. The periodic error detection circuit of claim 7, wherein

the module is a vector engine executing calculation on vector control of a motor and the peripheral module is a motor control circuit controlling motor driving.

10. The periodic error detection circuit of claim 9, wherein

the motor control circuit performs a first interruption to the processor when the periodic triggers are output, the processor enables the vector engine corresponding to the first interruption, and the vector engine performs a second interruption to the processor when the processing is completed.

11. A periodic error detection circuit, comprising:

a peripheral module outputting periodic triggers with an predetermined interval;

a processor controlling periodic processing by booting a peripheral module and executes a periodic error detection program to determine whether the periodic processing error occurs;

a module, execution of processing of the module being controlled by the processor;

a capture timer including a counter and a resister, the counter performing an up-count operation with free-run, the resister storing a first count value, the first count value being acquired from the counter by outputting the periodic triggers as a first capture trigger, storing a second count value, the second count value being acquired from the counter by outputting a second capture trigger when the processing of the module is started, and storing a third count value, the third count value being acquired from the counter by outputting a third capture trigger when the processing of the module is completed; and

12. The periodic error detection circuit of claim 11, wherein

the periodic error detection program calculating an added value in which a first value and a second value are added as the processing time, the first value is subtracted the first count value from the second count value and the second value is subtracted the second count value from the third count value, and the added value is compared with the predetermined interval to determine whether the periodic processing error occurs.

13. The periodic error detection circuit of claim 11, wherein

the module is a vector engine executing calculation on vector control of a motor and the peripheral module is a motor control circuit controlling motor driving.

14. The periodic error detection circuit of claim 13, wherein

the motor control circuit performs a first interruption to the processor when the periodic triggers are output, the processor enables the vector engine corresponding to the first interruption, and the vector engine performs a second interruption to the processor when the processing is completed.