METHODS AND APPARATUS TO PERFORM ERROR DETECTION AND CORRECTION

• US 20130111295A1
• Filed: 10/31/2011
• Published: 05/02/2013
• Est. Priority Date: 10/31/2011
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Jouppi, Norman Paul, Muralimanohar, Naveen, Li, Sheng
• Granted Patent: US 8,788,904 B2
• Time in Patent Office: Days
• US Class Current: 714/755
• CPC Class Codes: G06F 11/1064 in cache or content addressable memories

Abstract

Example methods, apparatus, and articles of manufacture to perform error detection and correction are disclosed. A disclosed example method involves enabling a memory controller to operate in one of a tagged memory mode or a non-tagged memory mode. In addition, when the tagged memory mode is enabled in the memory controller, a five-error-correction-six-error-detection per-burst mode is selected to perform error correction on data. When the non-tagged memory mode is enabled in the memory controller, one of a six-error-correction-seven-error-detection per-burst mode or a single-error-correction-dual-error-detection per-transfer mode is selected based on a pattern of error types in the data.

Claims

1. A method to perform error detection and correction, the method comprising:

enabling a memory controller to operate in one of a tagged memory mode or a non-tagged memory mode;

when the tagged memory mode is enabled in the memory controller, selecting a five-error-correction-six-error-detection per-burst mode to perform error correction on data; and

when the non-tagged memory mode is enabled in the memory controller, selecting one of a six-error-correction-seven-error-detection per-burst mode or a single-error-correction-dual-error-detection per-transfer mode based on a pattern of error types in the data.

2. A method as defined in claim 1, wherein the memory controller is to operate in one of the tagged memory mode or the non-tagged memory mode based on a setting in a system memory mode register of the memory controller.

3. A method as defined in claim 1, further comprising, when the tagged memory mode is enabled in the memory controller, retrieving a number of bytes of data, a number of bits of an error correction code, and extension bits corresponding to a tagged extended double word from a non-tag-specific memory into the memory controller within a single read cycle.

4. A method as defined in claim 1, further comprising, when the tagged memory mode is enabled in the memory controller:

using a fast error correction code process to correct an error when the memory controller detects one error in the data or extension bits;

using a slow error correction code process to correct errors when the memory controller detects two or three errors in the data or the extension bits; and

using a slowest error correction code process to correct errors when the memory controller detects more than three errors in the data or the extension bits.

5. A method as defined in claim 1, further comprising, when the tagged memory mode is enabled in the memory controller, using a first portion of bits reserved for an error correction code to store extension bits for tagged memory words, and using a second portion of the bits reserved for the error correction code to store the error correction code.

6. A method as defined in claim 5, wherein the first portion of the bits reserved for the error correction code includes eight bits corresponding to sixty-four-bit words, and wherein the second portion of the bits reserved for the error correction code includes fifty-one bits corresponding to the sixty-four-bit words.

7. An apparatus to perform error detection and correction, the apparatus comprising:

a tagged mode selector to dynamically enable a memory controller to operate in a tagged memory mode; and

an error correction mode selector to;

select a fast error correction code process to correct an error when the memory controller detects one error in data or extension bits;

select a slow error correction code process to correct errors when the memory controller detects two or three errors in the data or the extension bits; and

select a slowest error correction code process to correct errors when the memory controller detects more than three errors in the data or the extension bits.

8. An apparatus as defined in claim 7, wherein the error correction mode selector is to select a five-error-correction-six-error-detection per-burst mode to perform error correction on the data or the extension bits.

9. An apparatus as defined in claim 7, wherein the error correction mode selector is to select one of a six-error-correction-seven-error-detection per-burst mode or a single-error-correction-dual-error-detection per-transfer mode based on error types in the data when the tagged mode selector enables a non-tagged memory mode in the memory controller.

10. An apparatus as defined in claim 7, further comprising a system memory mode register to indicate whether to set the memory controller to operate in the tagged memory mode or a non-tagged memory mode.

11. An apparatus as defined in claim 7, further comprising logic to perform a fast error correction code process, a slow error correction code process, or a slowest error correction code process on the data and the extension bits retrieved from a non-tag-specific memory.

12. A tangible machine accessible medium having instructions stored thereon that, when executed, cause a machine to at least:

enable a memory controller to operate in one of a tagged memory mode or a non-tagged memory mode;

when the tagged memory mode is enabled in the memory controller, selecting a five-error-correction-six-error-detection mode to perform error correction on data or extension bits; and

when the non-tagged memory mode is enabled in the memory controller, selecting one of a six-error-correction-seven-error-detection mode or a single-error-correction-dual-error-detection mode based on a pattern of error types in the data or the extension bits.

13. A machine accessible medium as defined in claim 12, wherein the instructions cause the memory controller to operate in one of the tagged memory mode or the non-tagged memory mode based on a setting in a system memory mode register of the memory controller.

14. A machine accessible medium as defined in claim 12, having instructions stored thereon that, when executed, cause the machine to, when the tagged memory mode is enabled in the memory controller, use a first portion of bits reserved for an error correction code to store extension bits for tagged memory words, and use a second portion of the bits reserved for the error correction code to store a number of error correction code bits corresponding to the tagged memory words.

15. A machine accessible medium as defined in claim 14 having instructions stored thereon that, when executed, cause the machine to:

use a fast error correction code process to correct an error when the memory controller detects one error in the data or extension bits;

use a slow error correction code process to correct errors when the memory controller detects two or three errors in the data or the extension bits; and

use a slowest error correction code process to correct errors when the memory controller detects more than three errors in the data or the extension bits.