THIN-FILM TRANSISTOR ARRAY SUBSTRATE, ORGANIC LIGHT-EMITTING DISPLAY INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME

• US 20130112976A1
• Filed: 06/18/2012
• Published: 05/09/2013
• Est. Priority Date: 11/08/2011
• Status: Abandoned Application

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Mobile Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Lee, Dae-Woo, Choi, Jong-Hyun, Kim, Byoung-Ki
• Application Number:
  US13/526,257
• Publication Number:
  US 20130112976A1
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H10K 19/10 comprising field-effect transistors
• CPC Class Codes: H10K 59/124 Insulating layers formed between TFT elements and OLED elements
• CPC Class Codes: H10K 59/179 Interconnections, e.g. wiring lines or terminals

Abstract

A thin-film transistor array substrate is disclosed. In one embodiment, the substrate includes: i) a thin-film transistor including an active layer, and gate, source and drain electrodes, ii) a lower electrode of a capacitor, iii) an upper electrode of the capacitor formed on the lower electrode iv) a first insulation layer between the lower and upper electrodes, and between the active layer and the gate electrode, and having a gap outside the lower electrode. The substrate may further include i) a second insulation layer formed on the first insulation layer and having the same etching surface as the first insulation layer in the gap, ii) a bridge formed of the same material as the source and drain electrodes, and filling a part of the gap and iii) a third insulation layer covering the source and drain electrodes and exposing a pixel electrode.

Claims

1. A thin-film transistor array substrate comprising:

a thin-film transistor comprising an active layer, a gate electrode, a source electrode, and a drain electrode;

a lower electrode of a capacitor formed of the same layer as the active layer;

an upper electrode of the capacitor formed on the lower electrode;

a first insulation layer formed between the lower and upper electrodes, and formed between the active layer and the gate electrode, wherein a gap is formed outside the lower electrode;

a second insulation layer formed on the first insulation layer and having the same etching surface as the first insulation layer in the gap;

a bridge formed of the same material as at least one of the source and drain electrodes, wherein the bridge at least partially fills the gap;

a pixel electrode formed of the same material as the upper electrode; and

a third insulation layer covering the source and drain electrodes, wherein an opening is defined in the third insulation layer, and wherein at least part of the pixel electrode is formed in the opening.

2. The thin-film transistor array substrate of claim 1, wherein the active layer and the lower electrode are formed of an ion impurity-doped semiconductor material.

3. The thin-film transistor array substrate of claim 1, wherein the upper electrode and the pixel electrode are formed of a transparent conductive material.

4. The thin-film transistor array substrate of claim 3, wherein the transparent conductive material comprises at least one selected from the group consisting of an indium tin oxide (ITO), an indium zinc oxide (IZO), a zinc oxide (ZnO), an indium oxide (In2O3), an indium gallium oxide (IGO), and an aluminum zinc oxide (AZO).

5. The thin-film transistor array substrate of claim 1, further comprising:

a first connector connected to the lower electrode; and

a second connector connected to the upper electrode,

wherein a first portion of the gap is formed between the lower electrode and the first connector, and wherein a second portion of the gap is formed in the first insulation layer formed outside the lower electrode.

6. The thin-film transistor array substrate of claim 5, wherein the bridge is formed in the second portion of the gap.

7. The thin-film transistor array substrate of claim 5, wherein the first connector is formed of the same material as the lower electrode.

8. The thin-film transistor array substrate of claim 5, wherein the second connector is formed of the same material as the upper electrode.

9. The thin-film transistor array substrate of claim 8, wherein the second connector is formed on and connected to the bridge formed in the second portion of the gap and the second insulation layer.

10. The thin-film transistor array substrate of claim 9, further comprising a wire formed of the same material as the source and drain electrodes between the second connector and the second insulation layer, wherein the wire directly contacts the second connector.

11. The thin-film transistor array substrate of claim 5, further comprising a protection film formed in the first portion of the gap.

12. The thin-film transistor array substrate of claim 11, wherein the protection film is formed of the same material as the source and drain electrodes.

13. The thin-film transistor array substrate of claim 11, wherein the protection film is formed of the same material as the upper electrode.

14. The thin-film transistor array substrate of claim 11, wherein the protection film is electrically insulated from the upper electrode.

15. The thin-film transistor array substrate of claim 1, wherein the third insulation layer contacts the upper electrode.

16. An organic light-emitting display comprising:

a thin-film transistor comprising an active layer, a gate electrode, a source electrode, and a drain electrode;

a lower electrode of a capacitor formed of the same layer as the active layer;

an upper electrode of the capacitor formed on the lower electrode;

a first insulation layer formed between the lower and upper electrodes, and formed between the active layer and the gate electrode, wherein a gap is formed outside the lower electrode;

a second insulation layer formed on the first insulation layer and having the same etching surface as the first insulation layer;

a bridge formed of the same material as the source and drain electrodes, wherein the bridge at least partially fills the gap;

a pixel electrode formed of the same material as the upper electrode;

a third insulation layer covering the source and drain electrodes, wherein an opening is defined in the third insulation layer, and wherein at least part of the pixel electrode is formed in the opening;

an organic light-emitting layer formed on the pixel electrode; and

a counter electrode formed on the organic light-emitting layer.

17. The organic light-emitting display of claim 16, wherein the counter electrode is a reflective electrode configured to reflect light emitted from the organic light-emitting layer.

18. The organic light-emitting display of claim 16, wherein the pixel electrode is formed of a transparent conductive material.

19. The organic light-emitting display of claim 18, wherein the pixel electrode further comprises a semi-transmission layer formed of a semi-transmission material.

20. A method of manufacturing a thin-film transistor array substrate, the method comprising:

forming a semiconductor layer on a substrate and forming an active layer of a thin-film transistor and a lower electrode of a capacitor by patterning the semiconductor layer;

forming a first insulation layer, forming a first metal layer on the first insulation layer, and forming an etch stop layer corresponding to the lower electrode and a gate electrode corresponding to a portion of the active layer based on patterning the first metal layer;

forming a second insulation layer, and etching the first and second insulation layers such that a gap exposing the etch stop layer and an opening exposing a portion of the active layer are formed;

forming a second metal layer, and forming a bridge filing a portion of the gap and source and drain electrodes substantially filling the opening of the active layer based on patterning the second metal layer;

forming a third metal layer, and forming a pixel electrode and an upper electrode of the capacitor based on patterning the third metal layer; and

forming a third insulation layer, and forming an opening which exposes the pixel electrode.

21. The method of claim 20, further comprising doping an ion impurity after forming the etch stop layer.

22. The method of claim 20, wherein the etch stop layer is removed while forming the second insulation layer and etching the first and second insulation layers.

23. The method of claim 20, further comprising doping an ion impurity after forming the source and drain electrodes.

24. The method of claim 20, further comprising, while forming the semiconductor layer, the active layer and the lower electrode, forming a first connector connected to the lower electrode based on patterning the semiconductor layer.

25. The method of claim 24, further comprising, while forming the second insulation layer and etching the first and second insulation layers, forming i) a first portion of the gap between the lower electrode and the first connector, and ii) a second portion of the gap in the first insulation layer which is formed outside the lower electrode.

26. The method of claim 25, wherein the bridge is formed in the second portion of the gap while forming the second metal layer, the bridge, and the source and drain electrodes.

27. The method of claim 26, further comprising, while forming the third metal layer, the pixel electrode and the upper electrode, forming a second connector connected to the upper electrode based on patterning the third metal layer, wherein the second connector is formed on the bridge.

28. The method of claim 23, further comprising, while forming the second metal layer, the bridge, and the source and drain electrodes, forming a protection film in the first portion of the gap based on the second metal layer.

29. The method of claim 23, further comprising, while forming the third metal layer, the pixel electrode and the upper electrode, forming a protection film in the first portion of the gap based on the third metal layer.