Variable Capacitor Circuit and Method

• US 20130113549A1
• Filed: 11/07/2012
• Published: 05/09/2013
• Est. Priority Date: 11/08/2011
• Status: Active Grant

• Current Assignee: IMEC International
• Original Assignee: IMEC International
• Inventors: Van Helleputte, Nick
• Granted Patent: US 9,610,044 B2
• Time in Patent Office: Days
• US Class Current: 327/541
• CPC Class Codes: A61B 5/0531 Measuring skin impedance
• CPC Class Codes: A61B 5/316 Modalities, i.e. specific diagnostic methods
• CPC Class Codes: A61B 5/346 Analysis of electrocardiograms
• CPC Class Codes: A61B 5/7214 using signal cancellation, e.g. based on input of two identical physiological sensors spaced apart, or based on two signals derived from the same sensor, for different optical wavelengths
• CPC Class Codes: H01L 27/0811 MIS diodes
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 2200/213 A variable capacitor being added in the input circuit, e.g. base, gate, of an amplifier stage
• CPC Class Codes: H03F 2200/261 Amplifier which being suitable for instrumentation applications
• CPC Class Codes: H03F 2203/45538 the IC comprising balancing means, e.g. trimming means
• CPC Class Codes: H03F 2203/45544 the IC comprising one or more capacitors, e.g. coupling capacitors
• CPC Class Codes: H03F 2203/45548 the IC comprising one or more capacitors as shunts to earth or as short circuit between inputs
• CPC Class Codes: H03F 2203/45576 the IC comprising input impedance adapting or controlling means
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit

Abstract

A variable capacitor circuit is disclosed. The variable capacitor circuit includes a plurality of MOS capacitors, each MOS capacitor being implemented by a MOS transistor with the gate terminal connected to a first voltage signal and with the drain terminal shorted with the source terminal and connected to a second voltage signal, said MOS capacitors being connected in parallel through the gate terminal connected to the first voltage signal, and being operated in a cut-off region in which the equivalent capacitance of each MOS capacitor remains substantially constant for variations of the first voltage signal.

Claims

1. A variable capacitor circuit comprising:

a plurality of MOS capacitors, each MOS capacitor being implemented by a MOS transistor with the gate terminal connected to a first voltage signal and with the drain terminal shorted with the source terminal and connected to a second voltage signal, said MOS capacitors being connected in parallel through the gate terminal connected to the first voltage signal, and being operated in a cut-off region in which equivalent capacitance of each MOS capacitor remains substantially constant for variations of the first voltage signal.

2. The variable capacitor circuit of claim 1, wherein the value of the second voltage signal is restricted to two voltage values lying within the cut-off region.

3. The variable capacitor circuit of claim 2, wherein said values of the second voltage signal are selected from the group consisting of 0V and 0.5V.

4. The variable capacitor circuit of claim 2, wherein said two values are chosen such that the equivalent capacitance of each MOS capacitor varies in the sub femtoFarad range.

5. The variable capacitor circuit of claim 2, wherein a total equivalent capacitance of the variable capacitor circuit is controlled by a digital signal.

6. The variable capacitor circuit of claim 1, wherein the MOS capacitors of the variable capacitor circuit are implemented with binary scaled sizes such that the equivalent capacitance of the MOS capacitors follows a binary arrangement.

7. The variable capacitor circuit of claim 1, wherein the MOS transistor is a pMOs transistor and is operated for first voltage signals close to a ground rail satisfying the cut-off requirement.

8. The variable capacitor circuit of claim 1, wherein the MOS transistor is an nMOs transistor and is operated for first voltage signals close to a positive supply rail.

11. A method for compensating a capacitance mismatch between the input lines of an instrumentation amplifier, the method comprising:

connecting a variable capacitor circuit according to claim 1 to each input line of the instrumentation amplifier and changing the equivalent capacitance of the variable capacitor circuit so as to balance the parasitic loads on both input lines.

12. The method of claim 11, wherein changing the equivalent capacitance of the variable capacitor circuit comprises applying a digital signal to variable capacitor circuit.

9. A biomedical signal acquisition circuit comprising:

an instrumentation amplifier, the instrumentation amplifier comprising at least one input line; and

a variable capacitor circuit connected to each of the at least one input line of the instrumentation amplifier, wherein the variable capacitor circuit comprises a plurality of MOS capacitors, each MOS capacitor being implemented by a MOS transistor with the gate terminal connected to a first voltage signal and with the drain terminal shorted with the source terminal and connected to a second voltage signal, said MOS capacitors being connected in parallel through the gate terminal connected to the first voltage signal, and being operated in a cut-off region in which equivalent capacitance of each MOS capacitor remains substantially constant for variations of the first voltage signal.

10. The biomedical signal acquisition circuit of claim 9, wherein the variable capacitor circuit is connected to the input line of the instrumentation amplifier through the first voltage signal terminal