Methods and apparatus for suppression of low-frequency noise and drift in wireless sensors or receivers

• US 20130113650A1
• Filed: 05/01/2012
• Published: 05/09/2013
• Est. Priority Date: 05/04/2011
• Status: Active Grant

• Current Assignee: SaberTek, Inc.
• Original Assignee: SaberTek, Inc.
• Inventors: Behbahani, Farbod, Jain, Vipul
• Granted Patent: US 8,552,902 B2
• Time in Patent Office: Days
• US Class Current: 342/27
• CPC Class Codes: G01S 11/06 using intensity measurements
• CPC Class Codes: G01S 13/88 Radar or analogous systems specially adapted for specific applications electromagnetic prospecting or detecting of objects, e.g. near-field detection, G01V3/00
• CPC Class Codes: G01S 13/89 for mapping or imaging
• CPC Class Codes: G01S 7/2926 by integration

Abstract

An imaging receiver includes a low noise amplifier (LNA) module to receive and amplify the radio-frequency (RF) input signal; one or more switches configured to selectively pass RF input to one or more of the power detector circuits; one or more power detector circuits coupled to the switches to generate output voltages proportional to associated powers at their input ports; one or more reference circuits to provide reference signals to the switches; and one or more integrator circuits to integrate the output voltages of the power detector circuits.

Claims

1. An imaging receiver, comprising:

a low noise amplifier (LNA) module to receive and amplify e radio-frequency (RF) input signal;

one or more switches configured to selectively pass RF input to one or more of the power detector circuits;

one or more power detector circuits coupled to the switches to generate output voltages proportional to associated powers at their input ports;

one or more reference circuits to provide reference signals to the switches; and

one or more integrator circuits to integrate the output voltages of the power detector circuits.

2. The receiver of claim 1, further comprising a clock generator to produce timing signals and events for the switch(es) and integrator circuits.

3. The imaging receiver of claim 2, wherein the switches comprise single-pole double-throw (SPDT) switches.

4. The receiver of claim 3, comprising a circuit for cancellation or reduction of flicker noise and drift to improve thermal sensitivity.

5. The receiver of claim 3, wherein each SPDT switch is alternately switched between two states using a clock as a digital control signal.

6. The imaging receiver of claim 3, wherein:

a first input of a first SPDT switch is coupled to the output of the LNA module, a second input connected to an output of a reference circuit, the output connected to the input of a first power detector circuit;

a first input of a second SPDT switch is connected to the output of the LNA module, the second input connected to an output of a reference circuit, the output connected to the input of a second power detector circuit;

during a first phase of a control clock, the first input of the first SPDT switch is connected to the output of the first SPDT switch, and the second input of the second switch is connected to the output of the second SPDT switch; and

during a second phase of the control clock, the second input of the first SPDT switch is connected to the output of the first SPDT switch, and the first input of the second switch is connected to the output of the second SPDT switch.

7. The imaging receiver of claim 3, further comprising:

a power splitter having an input and two outputs, with the input connected to the output of the LNA module;

a first amplifier with an input connected to a first output of the power splitter; and

a second amplifier with an input connected to a second output of the power splitter.

8. The imaging receiver of claim 7, further comprising:

a first SPDT switch in a bias circuit path of the first amplifier, with a first input connected to a first voltage level, a second input connected to a second voltage level, and an output connected to a bias terminal of the first amplifier;

a second SPDT switch in a bias circuit path of the second amplifier, with a first input connected to a first voltage level, a second input connected to a second voltage level, and an output connected to a bias terminal of the second amplifier;

during a first phase of a control clock, the first input of the first SPDT switch is connected to the output of the first SPDT switch, and the second input of the second SPDT switch is connected to the output of the second SPDT switch; and

during a second phase of the control clock, the second input of the first SPDT switch is connected to the output of the first SPDT switch, and the first input of the second SPDT switch is connected to the output of the second SPDT switch.

9. The imaging receiver of claim 3, further comprising:

an SPDT switch, with its input connected to the output of the LNA module, a first output connected to the input of a first amplifier, and a second output connected to the input of a second amplifier;

a first amplifier with its input connected to the first output of the SPDT switch, and its output connected to the input of a first power detector circuit;

a second amplifier with its input connected to the second output of the SPDT switch, and its output connected to the input of a second power detector circuit.

during a first phase of a control clock, the input of the SPDT switch is connected to the first output of the SPDT switch; and

during a second phase of the control clock, the input of the SPDT switch is connected to the second output of the SPDT switch.

10. The imaging receiver of claim 3, further comprising:

a voltage combiner circuit coupled to the two power detector circuit outputs; and

a subtractor circuit following the power detector circuits.

11. The imaging receiver of claim 3, wherein the SPDT switches comprise current-steering switches.

12. The imaging receiver of claim 1, wherein the reference circuits comprise resistors, whose value are fixed, continuously variable, or variable in discrete steps.

13. The imaging receiver of claim 12, wherein the reference circuits further comprise one or more amplifiers, whose gain may be fixed, continuously variable, or variable in discrete steps.

14. The imaging receiver of claim 1, wherein the reference circuit includes an amplifier identical to the LNA module.

15. The imaging receiver of claim 1, wherein the reference circuit is shared between the switches and comprises:

an oscillator; and

a level adjustment circuit connected to an output of the oscillator and configured to adjust a level of a reference signal, wherein the level adjustment circuit includes a combination of active and passive components.

16. The receiver of claim 1, wherein the integrator circuit simultaneously performs a function of a subtractor circuit,

17. The receiver of claim 1, further comprising:

one or more baseband amplifiers;

an anti-aliasing filter;

a sample-and-hold circuit; and

an accumulator circuit.

18. The receiver of claim 1, further comprising an analog-to-digital converter (ADC) to convert the output analog voltage signal into digital bits.

19. The receiver of claim 1, wherein the receiver is formed completely or partially on one or more integrated circuit chips.

20. The receiver of claim 1, wherein the receiver is mounted on a high-frequency substrate through flip-chip technology, said high-frequency substrate comprising:

a. a feed line connected to the RF input of the receiver; and

b. a transition from the feed line to a waveguide flange.

21. The receiver of claim 1 , further comprising a calibration module to calibrate several characteristics of the receiver selected from the group consisting of:

gains of constituent amplifiers, the values of constituent resistors, currents and voltage in constituent bias circuits, noise temperature (or noise power) of the reference circuit, a digital clock frequency, a duty cycle of a digital control clock in the receiver, and accuracy of cancellation/reduction of flicker noise and drift in the receiver.

22. An imaging receiver array, comprising a plurality of receivers of claim 1, with inputs connected to a plurality of antennas, and with each output generating a pixel in the image.

25. The method of claim 22, further comprising calibrating the receiver by adjusting a power level of the reference signal.

23. A method for imaging using a receiver on an integrated circuit chip, comprising:

amplifying a radio-frequency (RF) signal at a receiver input, by passing the signal through a low noise amplifier (LNA) module;

generating a reference signal;

generating an output representative of the power of the RF signal, during a first phase of a control clock, and of the reference signal, during a second phase of the control clock; and

generating another output representative of the power of the reference signal, during the first phase of the control clock, and of the RI'"'"' signal, during the second phase of the control clock.

24. The method of claim 23, further comprising;

integrating a difference between output voltages of the two outputs during a clock cycle; and

sampling the result of the integration at the instants the control clock transitions from one phase to the other.