FLEXIBLE RECEIVER ARCHITECTURE

• US 20130114663A1
• Filed: 11/04/2011
• Published: 05/09/2013
• Est. Priority Date: 11/04/2011
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Peng Li, Sergey Shumarayev, Sriram Narayan, Weiqi Ding
• Inventors: SHUMARAYEV, Sergey, NARAYAN, Sriram, LI, Peng, DING, Weiqi
• Granted Patent: US 9,444,656 B2
• Time in Patent Office: Days
• US Class Current: 375/230
• CPC Class Codes: H04L 2025/03573 between recursive and non-recursive
• CPC Class Codes: H04L 25/03038 with a non-recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03146 with a recursive structure H04L25/03127 takes precedence

Abstract

One embodiment relates to a receiver circuit for a data link. The receiver circuit includes at least a first signal path, a second signal path, and a path selector circuit. The first signal path includes first equalization circuitry, and the second signal path includes second equalization circuitry. The path selector circuit is configured to select one signal path of the first and second signal paths. Other embodiments and features are also disclosed.

Claims

1. A receiver circuit for a data link, the receiver circuit comprising:

a first signal path including first equalization circuitry;

a second signal path including second equalization circuitry; and

a path selector circuit which is configured to select one signal path of the first and second signal paths.

2. The receiver circuit of claim 1, wherein the first signal path comprises a decision feedback equalizer circuit and the second signal path comprises linear equalization without decision feedback equalization.

3. The receiver circuit of claim 2, wherein the first signal path comprises a continuous-time linear estimation circuit in series with the decision feedback equalizer circuit.

4. The receiver circuit of claim 1, wherein the second signal path comprises at least one analog equalizer circuit.

5. The receiver circuit of claim 4, wherein the second signal path comprises a variable continuous-time linear estimation circuit.

6. The receiver circuit of claim 5, wherein the variable continuous-time linear estimation circuit is configured to boost a signal amplitude for a range of frequencies.

7. The receiver circuit of claim 4, wherein the second signal path comprises a series of continuous-time linear estimation circuits, including at least one variable continuous-time linear estimation circuit, wherein the variable continuous-time linear estimation circuit comprises a first node between a first transistor and a first current source, a second node between a second transistor and a second current source, and a resistor and a capacitor in parallel between the first and second nodes, wherein at least one of the resistor and the capacitor is variable.

8. The receiver circuit of claim 1, wherein the receiver circuit is configured to shut-off power to an un-selected signal path.

9. The receiver circuit of claim 1, further comprising:

a first analog equalizer circuit for receiving a data signal and for outputting the data signal to the first and second signal paths.

10. The receiver circuit of claim 9, further comprising:

a buffer circuit for providing the data signal to the first analog equalizer circuit; and

a clock data recovery circuit for receiving an equalized data signal from the path selector circuit.

11. An integrated circuit comprising:

a serial data receiver including multiple signal paths, each signal path including at least one equalization circuit; and

a path selector circuit which is configured to select one signal path of the multiple signal paths.

12. The integrated circuit of claim 11, wherein a first signal path comprises a decision feedback equalizer circuit, and a second signal path comprises linear equalization without decision feedback equalization.

13. The integrated circuit of claim 12, wherein the first signal path comprises a continuous-time linear estimation circuit in series with the decision feedback equalizer circuit.

14. The integrated circuit of claim 13, wherein the second signal path comprises a variable continuous-time linear estimation circuit.

15. The integrated circuit of claim 11, wherein the serial data receiver is configured to shut-off power to an un-selected signal path.

16. The integrated circuit of claim 11, wherein the integrated circuit comprises a field programmable gate array.

17. A method of receiver equalization, the method comprising:

providing an integrated circuit with a multiple-path receiver equalizer and a path selector circuit;

performing electronic programming to configure the path selector circuit to use a selected signal path for receiver equalization; and

performing equalization on received data using the selected signal path.

18. The method of claim 17, wherein a first signal path comprises a decision feedback equalization circuit and a second signal path comprises linear equalization without decision feedback equalization.

19. The method of claim 18, further comprising:

shutting off power to the decision feedback equalization circuit if the first signal path is not selected.

20. The method of claim 18, wherein a second signal path comprises a variable continuous-time linear estimation circuit.