METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

• US 20130115722A1
• Filed: 11/07/2012
• Published: 05/09/2013
• Est. Priority Date: 11/08/2011
• Status: Abandoned Application

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: NAKAGAWA, Hiroshi, TAKADA, Shigeru, TANAKA, Tamotsu
• Application Number:
  US13/671,208
• Publication Number:
  US 20130115722A1
• Time in Patent Office: Days
• US Class Current: 438/15
• CPC Class Codes: G01R 1/0466 concerning contact pieces or mechanical details, e.g. hinges or cams; Shielding
• CPC Class Codes: G01R 1/06722 Spring-loaded
• CPC Class Codes: G01R 1/06738 related to tip portion
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/32014 the layer connector being smaller than the bonding area, e.g. bond pad
• CPC Class Codes: H01L 2224/32055 being circular or elliptic
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85205 Ultrasonic bonding
• CPC Class Codes: H01L 2224/85207 Thermosonic bonding
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/15183 : in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

The manufacturing efficiency of semiconductor devices is improved. A plurality of external terminals (leads) electrically coupled with a semiconductor chip, and contact regions of a plurality of terminals (test terminals) are brought into contact with each other, respectively. This establishes an electrical coupling between the semiconductor chip and a test circuit. Thus, an electrical test is performed. Herein, the terminals are to be repeatedly used in the electrical test of a plurality of semiconductor devices. Whereas, the contact region of the terminal includes a core material formed of a first alloy, and a metal film covering the core material. Further, the metal film is formed of a second alloy higher in hardness than the first alloy.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of:

(a) preparing a base material including a chip mounting part and a plurality of external terminals;

(b) mounting a semiconductor chip including a plurality of electrode pads over the chip mounting part of the base material;

(c) electrically coupling the electrode pads of the semiconductor chip and the external terminals of the base material via a plurality of conductive members, respectively; and

(d) bringing the external terminals of the base material into contact with contact regions of a plurality of test terminals, thereby electrically coupling the semiconductor chip and a test circuit, and performing an electrical test,

each of the contact regions of the test terminals including a core material formed of a first alloy, and a metal film covering the core material, and

the metal film being formed of a second alloy higher in hardness than the first alloy.

2. The method for manufacturing a semiconductor device according to claim 1,

wherein each end of the contact regions of the test terminals is in a pointed shape, and

wherein in the step (d), the electrical test is performed with a part of the contact region of each of the test terminals biting into each of the external terminals.

3. The method for manufacturing a semiconductor device according to claim 2,

wherein the test terminals are repeatedly used for the electrical test of a plurality of semiconductor devices.

4. The method for manufacturing a semiconductor device according to claim 3,

wherein in the step (d), (d1) until the core material of the metal film is exposed, the metal film and each of the external terminals are brought into contact with each other, thereby to perform the electrical test, and (d2) after the core material is exposed, the core material and the external terminals are brought into contact with each other, thereby to perform the electrical test.

5. The method for manufacturing a semiconductor device according to claim 4,

wherein the first alloy forming the core material and the second alloy forming the metal film have a constituent element included in the largest content therein in common.

6. The method for manufacturing a semiconductor device according to claim 5,

wherein each surface of the external terminals is formed of a solder, and

wherein each of the first and second alloys is a palladium alloy including a palladium (Pd) element in the largest content among constituent elements.

7. The method for manufacturing a semiconductor device according to claim 6,

wherein each of the first and second alloys includes an element lower in electrical resistivity than the palladium (Pd) element.

8. The method for manufacturing a semiconductor device according to claim 5,

wherein the second alloy includes a cobalt (Co) element other than the palladium (Pd) element.

9. The method for manufacturing a semiconductor device according to claim 4,

wherein in the step (d), (d3) after repeated uses, the contact region of the core material is polished and sharpened, and then, the core material and each of the external terminals are brought into contact with each other, thereby to perform the electrical test.

10. The method for manufacturing a semiconductor device according to claim 9,

wherein when the contact region of the core material is polished, with a polishing jig pressed against a flat surface which is the to-be-polished surface of the core material, the polishing jig is vibrated along the flat surface.

11. The method for manufacturing a semiconductor device according to claim 10,

wherein when the contact region of the core material is polished, the polishing jig is vibrated in a plurality of directions crossing each other along the flat surface.

12. The method for manufacturing a semiconductor device according to claim 10,

wherein when the contact region of the core material is polished, the polishing jig is rotationally moved along the flat surface.

13. The method for manufacturing a semiconductor device according to claim 10,

wherein over the polishing surface of the polishing jig, an elastic body layer, and a polishing abrasive grain layer including a plurality of abrasive grains bonded thereover via a resin are successively stacked.

14. A method for manufacturing a semiconductor device, comprising the steps of:

(a) preparing a base material including a chip mounting part and a plurality of external terminals;

(b) mounting a semiconductor chip including a plurality of electrode pads over the chip mounting part of the base material;

(c) electrically coupling the electrode pads of the semiconductor chip and the external terminals of the base material via a plurality of conductive members, respectively; and

(d) bringing the external terminals of the base material into contact with contact regions of a plurality of test terminals, thereby electrically coupling the semiconductor chip and a test circuit, and performing an electrical test,

each surface of the external terminals being formed of a solder, and

the contact regions of the test terminals being formed of a palladium alloy including a palladium (Pd) element in the largest content among constituent elements.

15. The method for manufacturing a semiconductor device according to claim 14,

wherein each end of the contact regions of the test terminals is in a pointed shape, and

wherein in the step (d), the electrical test is performed with apart of the contact region of each of the test terminals biting into each of the external terminals.

16. The method for manufacturing a semiconductor device according to claim 15,

wherein the palladium alloy includes an element lower in electrical resistivity than the palladium (Pd) element.

17. The method for manufacturing a semiconductor device according to claim 16,

wherein the test terminals are repeatedly used for the electrical test of a plurality of semiconductor devices.

18. The method for manufacturing a semiconductor device according to claim 17,

wherein in the step (d), (d1) after repeated uses, the contact region of the core material is polished and sharpened, and then, the core material and each of the external terminals are brought into contact with each other, thereby to perform the electrical test.

19. The method for manufacturing a semiconductor device according to claim 18,

wherein when the contact region of the core material is polished, with a polishing jig pressed against a flat surface which is the to-be-polished surface of the core material, the polishing jig is vibrated along the flat surface.

20. The method for manufacturing a semiconductor device according to claim 19,

wherein when the contact region of the core material is polished, the polishing jig is vibrated in a plurality of directions crossing each other along the flat surface.

21. The method for manufacturing a semiconductor device according to claim 19,

wherein when the contact region of the core material is polished, the polishing jig is rotationally moved along the flat surface.

22. The method for manufacturing a semiconductor device according to claim 19,

wherein over the polishing surface of the polishing jig, an elastic body layer, and a polishing abrasive grain layer including a plurality of abrasive grains bonded thereover via a resin are successively stacked.