Vertical Gate LDMOS Device
First Claim
1. A method of fabricating a vertical gate region in a laterally diffused metal oxide semiconductor (LDMOS) transistor, the method comprising:
- depositing a first masking layer on an n-well region implanted on a substrate;
patterning the first masking layer to define an area;
depositing a second masking layer over the area;
etching through the second masking layer in a first portion of the area to expose the n-well region;
etching the exposed n-well region to form a first trench such that the first trench extends from a surface of the n-well region to a first depth in the n-well region;
filling the first trench with an oxide;
etching through the second masking layer in a second portion of the area to expose the n-well region;
forming a second trench in the n-well such that the second trench abuts the first trench and extends from the surface of the n-well region to a second depth in the n-well region, the second depth being less than the first depth; and
forming an asymmetric vertical gate of the LDMOS transistor by filling the second trench with a conductive material.
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Accused Products
Abstract
A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a first depth, is filled with an oxide. The second masking layer is etched through in a second portion of the area to expose the n-well region. A second trench is formed in the n-well, the second trench extending from the surface to a second depth, less than the first depth. An asymmetric vertical gate is formed by filling the second trench with a conductive material.
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Citations
14 Claims
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1. A method of fabricating a vertical gate region in a laterally diffused metal oxide semiconductor (LDMOS) transistor, the method comprising:
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depositing a first masking layer on an n-well region implanted on a substrate; patterning the first masking layer to define an area; depositing a second masking layer over the area; etching through the second masking layer in a first portion of the area to expose the n-well region; etching the exposed n-well region to form a first trench such that the first trench extends from a surface of the n-well region to a first depth in the n-well region; filling the first trench with an oxide; etching through the second masking layer in a second portion of the area to expose the n-well region; forming a second trench in the n-well such that the second trench abuts the first trench and extends from the surface of the n-well region to a second depth in the n-well region, the second depth being less than the first depth; and forming an asymmetric vertical gate of the LDMOS transistor by filling the second trench with a conductive material. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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Specification