LOW OVERHEAD OPERATION LATENCY AWARE SCHEDULER

• US 20130117543A1
• Filed: 11/04/2011
• Published: 05/09/2013
• Est. Priority Date: 11/04/2011
• Status: Abandoned Application

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Venkataramanan, Ganesh, Butler, Michael G.
• Application Number:
  US13/289,428
• Publication Number:
  US 20130117543A1
• Time in Patent Office: Days
• US Class Current: 712/220
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/382 Pipelined decoding, e.g. using predecoding
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking

Abstract

A method and apparatus for processing multi-cycle instructions include picking a multi-cycle instruction and directing the picked multi-cycle instruction to a pipeline. The pipeline includes a pipeline control configured to detect a latency and a repeat rate of the picked multi-cycle instruction and to count clock cycles based on the detected latency and the detected repeat rate. The method and apparatus further include detecting the repeat rate and the latency of the picked multi-cycle instruction, and counting clock cycles based on the detected repeat rate and the latency of the picked multi-cycle instruction.

Claims

1. A method of processing a multi-cycle instruction comprising:

detecting a repeat rate and a latency of a first multi-cycle instruction; and

counting clock cycles based on the detected repeat rate and the detected latency of the first multi-cycle instruction.

2. The method according to claim 1, further comprising:

directing the multi-cycle instruction to a pipeline.

3. The method according to claim 2, wherein the pipeline includes a pipeline control configured to perform the detecting and counting.

4. The method according to claim 2 further comprising:

directing the result of the first multi-cycle instruction to another pipeline executing a dependent instruction, on a condition that the dependent instruction is executed in the other pipeline in the same clock cycle that a result of the first multi-cycle instruction is distributed.

5. The method according to claim 1 further comprising

indicating that a second multi-cycle instruction is not eligible to be processed for a duration of the repeat rate of the first multi-cycle instruction.

6. The method according to claim 1 further comprising:

indicating that a second multi-cycle instruction is eligible to be picked on a condition that a count of the repeat rate of the first multi-cycle instruction has expired.

7. The method according to claim 1 further comprising:

broadcasting a destination address where a result of the first instruction is stored.

8. The method according to claim 7, wherein the broadcasting occurs a predetermined number of cycles before the result is to be distributed.

9. The method according to claim 1 further comprising:

indicating, a predetermined number of cycles before a result of the first multi-cycle instruction is distributed, that a single cycle instruction is not eligible to be picked.

10. An apparatus for processing multi-cycle instructions comprising:

a pipeline configured to process multi-cycle instructions; and

a pipeline control configured to detect a latency and a repeat rate for each multi-cycle instruction and to count clock cycles based on the detected latency and the detected repeat rate.

11. The apparatus according to claim 10, further comprising:

a scheduler queue configured to queue a plurality of instructions for pipeline processing;

a picker configured to pick a multi-cycle instruction from the scheduler queue and to direct the picked multi-cycle instruction to the pipeline for processing; and

wherein the pipeline control is further configured to indicate whether the pipeline is eligible for multi-cycle instruction processing based on the repeat rate of the picked multi-cycle instruction.

12. The apparatus according to claim 11, wherein the pipeline control is further configured to indicate whether a single cycle instruction is eligible to be picked a predetermined number of cycles before the result of the picked multi-cycle instruction is distributed

13. The apparatus according to claim 11, wherein the pipeline control is configured to broadcast a destination address where the result of the picked multi-cycle instruction is stored

14. The apparatus according to claim 13 wherein the broadcasting occurs a predetermined number of cycles before the result of the picked multi-cycle instruction is distributed

15. The apparatus according to claim 11 further comprising

a plurality of other pipelines configured to configured to process multi-cycle instructions, wherein each pipeline is configured to process an exclusive subset of multi-cycle instructions;

and

wherein the pipeline control is further configured to direct the result of the picked multi-cycle instruction executing a dependent instruction, on a condition that the dependent instruction is executed in the other pipeline in the same clock cycle that a result of the picked multi-cycle instruction is distributed.

16. A computer-readable storage medium storing a set of instructions for execution by one or more processors to process multi-cycle instructions, the set of instructions comprising:

a picking code segment for picking a multi-cycle instruction;

a directing code segment for directing the picked multi-cycle instruction to a pipeline;

a detecting code segment for detecting a repeat rate and a latency of the picked multi-cycle instruction;

a counting code segment for counting clock cycles based on the detected repeat rate and the detected latency of the picked multi-cycle instruction.

17. The computer-readable storage medium of claim 16, wherein the instructions are hardware description language (HDL) instructions used for the manufacture of a device.