MEMORY SYSTEM AND OPERATING METHOD THEREOF

• US 20130117620A1
• Filed: 04/18/2012
• Published: 05/09/2013
• Est. Priority Date: 11/04/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Jinman Han, Sang-Hyun Joo, Sangyong Yoon
• Inventors: JOO, Sang-Hyun, PARK, Kitae, YOON, Sangyong, HAN, Jinman
• Granted Patent: US 8,812,933 B2
• Time in Patent Office: Days
• US Class Current: 714/746
• CPC Class Codes: G06F 11/08 Error detection or correction by redundancy in data representation, e.g. by using checking codes
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1016 Error in accessing a memory location, i.e. addressing error
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: H03M 13/151 using error location or error correction polynomials
• CPC Class Codes: H03M 13/1525 Determination and particular use of error location polynomials
• CPC Class Codes: H03M 13/1545 Determination of error locations, e.g. Chien search or other methods or arrangements for the determination of the roots of the error locator polynomial

Abstract

A memory system includes a nonvolatile memory device and a memory controller configured to control the nonvolatile memory device and configured to provide the nonvolatile memory device with error flag information including error location information of an error of data read from the nonvolatile memory device.

Claims

1. A memory system comprising;

a nonvolatile memory device configured to read data, to receive error information, and to correct the read data according to the received error information; and

a controller having an interface unit configured to receive the read data, and having a unit configured to determine a location of an error bit of the received data such that the interface outputs the error information on the determined error bit location of the received data,

wherein the error information includes bits corresponding to bits of the read data, the bits of the error information include a bit representing an error of a bit of the read data, and a value of the bit of the read data is changed according to a value of the bit of the error information.

2. The memory system of claim 1, wherein the nonvolatile memory device outputs the read data to the controller and receives the error information from the controller.

3. The memory system of claim 1, wherein:

the controller outputs the error information to the nonvolatile memory device; and

the error information does not include the read data and corrected data of the read data.

4. The memory system of claim 1, wherein the nonvolatile memory device outputs the read data as randomized data to the controller, and receives the error information as non-randomized data from the controller.

5. The memory system of claim 1, wherein the nonvolatile memory device comprises a page buffer unit to store the read data after outputting the read data to the controller and when receiving the error information from the controller such that the stored read data is corrected according to the received error information.

6. The memory system of claim 1, wherein the error information does not correspond to all of the bits of the read data.

7. The memory system of claim 1, wherein the nonvolatile memory device changes the value of the bit corresponding to the value of the bit of the received error information as a changed bit and stores the changed bit and maintained bit as the corrected data.

8. The memory system of claim 1, wherein the nonvolatile memory device maintains values of bits which do not correspond to the error information and stores the corrected data having the bit with the changed value and the bits with the maintained values.

9. The memory system of claim 1, wherein the nonvolatile memory device comprises a single bit memory array and a multi bit memory array, reads the data from the single bit memory array, and stores the corrected data in the multi bit memory array.

10. The memory system of claim 1, wherein the nonvolatile memory device reads the data programmed using an SLC program method and stores the corrected data according to an MLC program method.

11. The memory system of claim 1, wherein the nonvolatile memory device receives the error information in a page unit from the controller.

12. The memory system of claim 1, wherein the read data and the error information have a same data size.

13. The memory system of claim 1, wherein the nonvolatile memory device receives the error information corresponding to the read data in a copying operation to copy the data from a first region to a second region thereof.

14. The memory system of claim 1, wherein the nonvolatile memory device activates the reading the data and the storing the corrected data according to the received error information in response to a command indicating a copy operation.

15. The memory system of claim 1, wherein the nonvolatile memory device comprises a page buffer latch configured to perform the correction of the bit with the error according to the error information in a page unit of the read data, and the page buffer latch is configured to store the read data, the error information, and the corrected data.

16. The memory system of claim 15, wherein the nonvolatile memory device performs a bit-by-bit comparison between the bits of the read data and the error information to correct the error bit of the read data according to one of an exclusive OR method and an exclusive NOR method.

17. The memory system of claim 1, wherein the bits of the error information include a second bit representing a non-error of another bit of the read data, and a value of the another bit of the read data is not changed according to a value of the second-bit of the error information.

18. A memory system comprising:

a nonvolatile memory device to output data; and

a controller having an interface unit configured to receive the data from the nonvolatile memory device, and having a unit configured to determine a location of an error bit of the received data such that the interface outputs information on the determined error bit location of the received data to the nonvolatile memory device.

19. The memory system of claim 18, wherein controller de-randomizes the received data to determine the location of the error bit from the received data and outputs the information without randomization.

20. The memory system of claim 18, wherein the controller comprises a randomizer/de-randomizer to de-randomize the received data, and the controller prevents the randomizer/de-randomizer to randomize the information.

21. The memory system of claim 18, wherein the nonvolatile memory device corrects the data according to the received error location information.

22. The memory system of claim 18, wherein the nonvolatile memory device comprises a region from which the data has been read and the nonvolatile memory device performs a refresh program on the region according to the corrected data.

23. The memory system of claim 18, wherein:

the nonvolatile memory device comprises a second region to store the corrected data; and

the second region is a multi-bit memory array.

24. The memory system of claim 18, wherein the information on the determined error bit location of the received data comprises an address of the determined error bit location of the received data such that the nonvolatile memory device corrects the data according to the address.

25. A memory system comprising:

a controller; and

a nonvolatile memory device comprising a first region having a single bit memory array to store data according to a first program method and a second region having a multi-bit memory array, and configured to read the data of each of a plurality of pages from the first region, and configured to output the data of each of the plurality of pages to the controller,

wherein the controller generates error location information of the data of each of the plurality of pages and outputs the error location information of the data of each of the plurality of pages to the nonvolatile memory device,

wherein the nonvolatile memory device corrects the data of each of the pages according to the error location information corresponding the data of each of the plurality of pages, and stores the corrected data of the plurality of the pages at once in the second region according to a second program method.

26. The memory system of claim 25, wherein the data comprises a plurality of pages having at least a first page and a second page, and the controller repeats receiving the data such that first error information is determined and output in response to the first page and such that second error information is determined and output in response to the second page.

27. The memory system of claim 25, wherein the nonvolatile memory device simultaneously reads the data and receives the error location information.

28. The memory system of claim 25, wherein the nonvolatile memory device comprises a buffer circuit to simultaneously store the read data and the received error location information.

29. The memory system of claim 25, wherein the nonvolatile memory device comprises a main buffer to store the read data and a cache buffer to receive the error location information to correct the stored data in the main buffer according to the error location information.

30. The memory system of claim 25, wherein the nonvolatile memory device comprises a main buffer to communicate with the first region and the second region to store the read data and the corrected data, and a cache buffer to communicate with the controller to receive the error location information.

31. The memory system of claim 25, wherein the nonvolatile memory device performs a flipping operation of flipping a bit of the read data according to the error location information to generate the corrected data.

32. The memory system of claim 25, wherein the multi-bit memory array of the second region comprises a 3-bit memory array.

33. The memory system of claim 25, wherein the second program method comprises a plurality of operations each to generate different voltages according to the corrected data to be stored in the multi-bit memory array of the second region.

34. The memory system of claim 25, wherein the second program method comprises a reprogram method to generate different voltages according to the corrected data to be stored in the multi-bit memory array of the second region.

35. The memory system of claim 25, wherein:

the information corresponds to one of portions of the read data;

the read data is repeatedly transmitted from the controller to the nonvolatile memory device;

a number of information are transmitted from the controller to the nonvolatile memory device until corresponding to all portions of the read data; and

the nonvolatile memory device corrects each portion of the data according to the corresponding information upon receiving the corresponding information.

36. The memory system of claim 25, further comprising:

a host apparatus having a functional unit and a terminal to be connectable to the controller to store data in the nonvolatile memory device.

37. The memory system of claim 25, wherein the host apparatus outputs the data generated from the functional unit to be stored in the nonvolatile memory device through the controller or receives the data from the nonvolatile memory device to be used in the functional unit.

38. The memory system of claim 25, wherein the host apparatus comprises at least one of a video camera, a television apparatus, an audio device, a game machine, an electronic music device, a cellular phone, a computer a personal digital assistant, a voice recorder, a mobile device, and a contactless smart card.