SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20130119376A1
• Filed: 11/01/2012
• Published: 05/16/2013
• Est. Priority Date: 11/11/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: SASAGAWA, Shinya, KURATA, Motomu, KUWABARA, Hideaki, TERASHIMA, Mari
• Granted Patent: US 8,796,682 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

To provide a highly reliable semiconductor device including a transistor using an oxide semiconductor. After a source electrode layer and a drain electrode layer are formed, an island-like oxide semiconductor layer is formed in a gap between these electrode layers so that a side surface of the oxide semiconductor layer is covered with a wiring, whereby light is prevented from entering the oxide semiconductor layer through the side surface. Further, a gate electrode layer is formed over the oxide semiconductor layer with a gate insulating layer interposed therebetween and impurities are introduced with the gate electrode layer used as a mask. Then, a conductive layer is provided on a side surface of the gate electrode layer in the channel length direction, whereby an Lov region is formed while maintaining a scaled-down channel length and entry of light from above into the oxide semiconductor layer is prevented.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of:

forming a source electrode layer and a drain electrode layer over an insulating surface;

forming an oxide semiconductor layer in a gap between the source electrode layer and the drain electrode layer by a coating method;

forming a gate insulating layer in contact with a top surface of the source electrode layer, the drain electrode layer, and the oxide semiconductor layer;

forming a gate electrode layer in a region overlapping with the oxide semiconductor layer with the gate insulating layer interposed therebetween;

introducing an impurity element into the oxide semiconductor layer with the gate electrode layer used as a mask, thereby forming in the oxide semiconductor layer a pair of impurity regions and a channel region sandwiched between the pair of impurity regions;

forming a conductive film covering the gate electrode layer;

forming an insulating layer over the conductive film;

processing the insulating layer, thereby forming a first sidewall insulating layer and a second sidewall insulating layer provided on a side surface of the gate electrode layer in a channel length direction with the conductive film interposed therebetween; and

etching the conductive film with the first sidewall insulating layer and the second sidewall insulating layer used as a mask, thereby forming a first conductive layer and a second conductive layer in contact with the side surface of the gate electrode layer in the channel length direction.

2. The method for manufacturing a semiconductor device, according to claim 1, further comprising the steps of:

forming an interlayer insulating layer covering the first sidewall insulating layer, the second sidewall insulating layer, and the gate electrode layer;

forming an opening in the interlayer insulating layer and the gate insulating layer so as to reach the source electrode layer or the drain electrode layer; and

forming a wiring layer in the opening.

3. The method for manufacturing a semiconductor device, according to claim 1, further comprising the steps of:

forming an interlayer insulating layer covering the first sidewall insulating layer, the second sidewall insulating layer, and the gate electrode layer;

forming an opening in the interlayer insulating layer and the gate insulating layer so as to reach the source electrode layer or the drain electrode layer; and

forming a wiring layer in the opening,

wherein a layer including an aluminum oxide film is formed as the interlayer insulating layer.

4. The method for manufacturing a semiconductor device, according to claim 1, wherein the oxide semiconductor layer comprises a material selected from indium, gallium, and zinc.

5. A method for manufacturing a semiconductor device, comprising the steps of:

forming a source electrode layer and a drain electrode layer over an insulating surface;

forming an oxide semiconductor layer in a gap between the source electrode layer and the drain electrode layer by a coating method, and then performing heat treatment on the oxide semiconductor layer;

forming a gate insulating layer in contact with a top surface of the source electrode layer, the drain electrode layer, and the oxide semiconductor layer;

forming a gate electrode layer in a region overlapping with the oxide semiconductor layer with the gate insulating layer interposed therebetween;

introducing an impurity element into the oxide semiconductor layer with the gate electrode layer used as a mask, thereby forming in the oxide semiconductor layer a pair of impurity regions and a channel region sandwiched between the pair of impurity regions;

forming a conductive film covering the gate electrode layer;

forming an insulating layer over the conductive film;

processing the insulating layer, thereby forming a first sidewall insulating layer and a second sidewall insulating layer provided on a side surface of the gate electrode layer in a channel length direction with the conductive film interposed therebetween; and

etching the conductive film with the first sidewall insulating layer and the second sidewall insulating layer used as a mask, thereby forming a first conductive layer and a second conductive layer in contact with the side surface of the gate electrode layer in the channel length direction.

6. The method for manufacturing a semiconductor device, according to claim 5, further comprising the steps of:

forming an interlayer insulating layer covering the first sidewall insulating layer, the second sidewall insulating layer, and the gate electrode layer;

forming an opening in the interlayer insulating layer and the gate insulating layer so as to reach the source electrode layer or the drain electrode layer; and

forming a wiring layer in the opening.

7. The method for manufacturing a semiconductor device, according to claim 5, further comprising the steps of:

forming an interlayer insulating layer covering the first sidewall insulating layer, the second sidewall insulating layer, and the gate electrode layer;

forming an opening in the interlayer insulating layer and the gate insulating layer so as to reach the source electrode layer or the drain electrode layer; and

forming a wiring layer in the opening,

wherein a layer including an aluminum oxide film is formed as the interlayer insulating layer.

8. The method for manufacturing a semiconductor device, according to claim 5, wherein the oxide semiconductor layer comprises a material selected from indium, gallium, and zinc.

9. A semiconductor device comprising:

a source electrode layer and a drain electrode layer;

an oxide semiconductor layer comprising a first impurity region, a second impurity region, and a channel region sandwiched between the first impurity region and the second impurity region, wherein a side surface of the first impurity region is in contact with the source electrode layer in a channel-length direction and a side surface of the second impurity region is in contact with the drain electrode layer in the channel-length direction;

a gate insulating layer over and in contact with the oxide semiconductor layer, the source electrode layer, and the drain electrode layer;

a gate electrode layer over the gate insulating layer, wherein the gate electrode layer overlaps with the channel formation region;

a conductive layer having a first portion in contact with a side surface of the gate electrode layer and a second portion in contact with an upper surface of the gate insulating layer, wherein at least part of the second portion overlaps with the source electrode layer and the drain electrode layer;

a sidewall insulating layer in contact with an outer side surface of the first portion and an upper surface of the second portion, wherein the sidewall insulating layer is not in contact with the gate electrode layer; and

wherein the source electrode layer has a tapered shape,

wherein the drain electrode layer has a tapered shape, and

wherein edge of the oxide semiconductor layer overlap with the source electrode layer, and

wherein edge of the oxide semiconductor layer overlap with the drain electrode layer.