TRENCH TYPE POWER TRANSISTOR DEVICE AND FABRICATING METHOD THEREOF

• US 20130119460A1
• Filed: 07/08/2012
• Published: 05/16/2013
• Est. Priority Date: 11/15/2011
• Status: Active Grant

• Current Assignee: Anpec Electronics Corporation
• Original Assignee: Anpec Electronics Corporation
• Inventors: Lin, Yung-Fa, Hsu, Shou-Yi, Wu, Meng-Wei, Chen, Main-Gwo, Chang, Chia-Hao, Chen, Chia-Wei
• Granted Patent: US 8,940,606 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0886 Shape
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/423 not carrying the current to be rectified, amplified or switched
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The present invention provides a trench type power transistor device including a substrate, an epitaxial layer, a doped diffusion region, a doped source region, and a gate structure. The substrate, the doped diffusion region, and the doped source region have a first conductivity type, and the substrate has an active region and a termination region. The epitaxial layer is disposed on the substrate, and has a second conductivity type. The epitaxial layer has a through hole disposed in the active region. The doped diffusion region is disposed in the epitaxial layer at a side of the through hole, and is in contact with the substrate. The doped source region is disposed in the epitaxial layer disposed right on the doped diffusion region, and the gate structure is disposed in the through hole between the doped diffusion region and the doped source region.

Claims

1. A trench type power transistor device, comprising:

a substrate having a first conductivity type, wherein the substrate has an active region and a termination region;

an epitaxial layer disposed on the substrate and having a second conductivity type different from the first conductivity type, wherein the substrate has at least a first through hole and at least a second through hole respectively penetrating the epitaxial layer, the first through hole is located in the active region, and the second through hole is located in the termination region;

a first doped diffusion region disposed in the epitaxial layer at one side of the first through hole and in directly contact with the substrate, wherein the first doped diffusion region has the first conductivity type;

a doped source region disposed in the epitaxial layer and right above the first doped diffusion region, wherein the doped source region has the first conductivity type;

a gate structure disposed in the first through hole between the first doped diffusion region and the doped source region;

a second doped diffusion region disposed on one side of the second through hole in the epitaxial layer and in direct contact with the substrate, wherein the second doped diffusion region has the first conductivity type; and

a terminal conductive layer disposed in the second through hole right above the second doped diffusion region.

2. The trench type power transistor device according to claim 1, further comprising a first isolation layer disposed in the first through hole below the gate structure, wherein the first isolation layer electrically isolates the first doped diffusion region from the gate structure.

3. The trench type power transistor device according to claim 1, wherein the gate structure comprises a gate conductive layer and a gate dielectric layer, and the gate dielectric layer is disposed between the gate conductive layer and the epitaxial layer.

4. The trench type power transistor device according to claim 1, further comprising a well disposed in the epitaxial layer above the first doped diffusion layer and the second doped diffusion layer, wherein the well has a second conductivity type.

5. The trench type power transistor device according to claim 1, further comprising a second isolation layer located in the second through hole below the terminal conductive layer.

6. The trench type power transistor device according to claim 1, wherein the first conductivity type is P-type and the second conductivity type is N-type.

7. A method for fabricating a trench type power transistor device, comprising:

providing a substrate having a first conductivity type, wherein the substrate has an active region and a termination region;

forming an epitaxial layer on the substrate, wherein the substrate has a second conductivity type different from the first conductivity type;

forming at least a first through hole and at least a second through hole in the epitaxial layer to penetrate the epitaxial layer respectively, wherein the first through hole is located in the active region and the second through hole is located in the termination region;

filling a dopant source layer into the first through hole and the second through hole respectively;

forming a first doped diffusion region in the epitaxial layer at one side of the first through hole and forming a second doped diffusion region in the epitaxial layer at one side of the second through hole, wherein the first doped diffusion region and the second doped diffusion region have the first conductivity type;

forming a gate structure in the first through hole; and

forming a doped source region in the epitaxial layer at one side of the first through hole, and the doped source region located right above the first doped diffusion region, wherein the doped source region has the first conductivity type and the gate structure is disposed between the first doped diffusion region and the doped source region.

8. The method for fabricating the trench type power transistor device according to claim 7, wherein the step for forming the first doped diffusion region and the second doped diffusion region further comprises steps for forming a first isolation layer in the first through hole and forming a second isolation layer in the second through hole.

9. The method for fabricating the trench type power transistor device according to claim 7, wherein the step for forming the gate structure comprises:

forming a third isolation layer above the epitaxial layer and on the sidewall of both the first through hole and the second through hole;

removing the third isolation layer located within the termination region;

forming a conductive layer on the third isolation layer and on the epitaxial layer located in the termination region, wherein the conductive layer is filled into the first through hole and the second through hole; and

removing both the third isolation layer and the conductive layer outside the first through hole and the second through hole so that the gate structure is formed in the first through hole and a terminal conductive layer is formed in the second through hole.

10. The method for fabricating the trench type power transistor device according to claim 9, wherein the third isolation layer, the first doped diffusion region and the second doped diffusion region are formed concurrently.

11. The method for fabricating the trench type power transistor device according to claim 7, wherein each of the dopant source layers comprises a plurality of dopants having the first conductivity type, and the step for forming the first doped diffusion region and the second doped diffusion region comprises a thermal drive-in process to diffuse the dopants into the epitaxial layer so that the first doped diffusion region and the second doped diffusion region are formed.

12. The method for fabricating the trench type power transistor device according to claim 7, wherein the dopant source layer comprises boron silicate glass (BSG).

13. The method for fabricating the trench type power transistor device according to claim 7, further comprising forming a well in the epitaxial layer between the step for forming the epitaxial layer and the step for forming the first through hole and the second through hole, wherein the well has the second conductivity type.

14. The method for fabricating the trench type power transistor device according to claim 7, wherein the first conductivity type is P-type and the second conductivity type is N-type.