TRENCH SILICIDE AND GATE OPEN WITH LOCAL INTERCONNECT WITH REPLACEMENT GATE PROCESS

• US 20130119474A1
• Filed: 11/14/2011
• Published: 05/16/2013
• Est. Priority Date: 11/14/2011
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Schultz, Richard T.
• Granted Patent: US 8,716,124 B2
• Time in Patent Office: Days
• US Class Current: 257/368
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate

Abstract

A semiconductor device fabrication process includes forming insulating mandrels over replacement metal gates on a semiconductor substrate with first gates having sources and drains and at least one second gate being isolated from the first gates. Mandrel spacers are formed around each insulating mandrel. The mandrels and mandrel spacers include the first insulating material. A second insulating layer of the second insulating material is formed over the transistor. One or more first trenches are formed to the sources and drains of the first gates by removing the second insulating material between the insulating mandrels. A second trench is formed to the second gate by removing portions of the first and second insulating materials above the second gate. The first trenches and the second trench are filled with conductive material to form first contacts to the sources and drains of the first gates and a second contact to the second gate.

Claims

1. A semiconductor device fabrication process, comprising:

providing a transistor comprising a plurality of replacement metal gates on a semiconductor substrate with first gates having sources and drains and at least one second gate being isolated from the first gates, wherein the transistor comprises gate spacers of a first insulating material around each first gate and a first insulating layer of a second insulating material between the gate spacers, and wherein at least some of the second insulating material overlies sources and drains of the first gates;

forming one or more insulating mandrels aligned over the gates, wherein the insulating mandrels comprise the first insulating material;

forming mandrel spacers around each insulating mandrel, wherein the mandrel spacers comprise the first insulating material;

forming a second insulating layer of the second insulating material over the transistor;

forming one or more first trenches to the sources and drains of the first gates by removing the second insulating material from portions of the transistor between the insulating mandrels;

forming a second trench to the second gate by removing portions of the first insulating material and the second insulating material above the second gate; and

filling the first trenches and the second trench with conductive material to form first contacts to the sources and drains of the first gates and a second contact to the second gate.

2. The process of claim 1, further comprising filling the first trenches and the second trench with conductive material in a single process.

3. The process of claim 1, wherein each insulating mandrel has approximately the same width as its underlying gate with each mandrel being at least as wide as its underlying gate.

4. The process of claim 1, wherein each mandrel spacer has a profile that slopes from being wider at the bottom to narrower at the top.

5. The process of claim 1, wherein at least a portion of each mandrel spacer is exposed in each of the first trenches.

6. The process of claim 1, wherein the edges of the insulating mandrels extend past the edges of the gates.

7. The process of claim 1, wherein the edges of the mandrel spacers extend past the edges of the gate spacers.

8. The process of claim 1, further comprising forming the first trenches to the sources and drains of the first gates by removing the second insulating material in a process selective to remove second insulating material but not first insulating material.

9. The process of claim 1, further comprising forming a thin layer of the second insulating material over the transistor prior to forming the insulating mandrels.

10. The process of claim 1, wherein the first contacts comprise a slope determined by a slope of the mandrel spacers.

11. The process of claim 1, further comprising planarizing the transistor after filling the first trenches and the second trench with conductive material.

12. The process of claim 1, wherein forming the first trenches and the second trench is accomplished using a CAD (computer-aided design) designed resist pattern that defines the first trenches and the second trench.

13. The process of claim 1, further comprising:

forming a third insulating layer over the transistor;

forming third trenches through the third insulating layer to the first contacts and the second contact by removing portions of the third insulating layer; and

forming local interconnects to the first contacts and the second contact by depositing conductive material in the third trenches formed through the third insulating layer.

14. The process of claim 1, further comprising removing portions of the first insulating material above the gate in a process selective to remove first insulating material but not second insulating material such that the trench is aligned to the gate.

15. A semiconductor device, comprising:

a plurality of replacement metal gates on a semiconductor substrate, wherein first gates have sources and drains and at least one second gate is isolated from the first gates;

gate spacers of a first insulating material around each first gate;

a first insulating layer of a second insulating material between the gate spacers, wherein at least some of the second insulating material overlies sources and drains of the first gates;

one or more insulating mandrels aligned over the gates, wherein the insulating mandrels comprise the first insulating material;

mandrel spacers around each insulating mandrel, wherein the mandrel spacers comprise the first insulating material;

one or more first contacts to the sources and drains of the first gates through the first insulating layer between the mandrel spacers;

a second contact to the at least one second gate through the first insulating material above the second gate;

a third insulating layer over the transistor; and

one or more local interconnects that contact the first contacts and the second contact through the third insulating layer.

16. The device of claim 15, wherein the second contact to the at least one second gate is through the mandrel above the second gate.

17. The device of claim 15, wherein each insulating mandrel has approximately the same width as its underlying gate with each mandrel being at least as wide as its underlying gate.

18. The device of claim 15, wherein each mandrel spacer has a profile that slopes from being wider at the bottom to narrower at the top.

19. The device of claim 15, wherein the first contacts have a profile that matches the slope of the mandrel spacers such that the first contacts are wider at the top than at the bottom

20. The device of claim 15, wherein the first contacts are not shorted to the gates.

21. The device of claim 15, wherein the third insulating layer comprises the second insulating material.

22. The device of claim 15, wherein the first gates are located in an active region of the semiconductor device and the second gate is located in an isolation region of the semiconductor device.

23. A computer readable storage medium storing a plurality of instructions which, when executed, generate one or more resist patterns useable in a semiconductor process that comprises:

providing a transistor comprising a plurality of replacement metal gates on a semiconductor substrate with first gates having sources and drains and at least one second gate being isolated from the first gates, wherein the transistor comprises gate spacers of a first insulating material around each first gate and a first insulating layer of a second insulating material between the gate spacers, and wherein at least some of the second insulating material overlies sources and drains of the first gates;

forming one or more insulating mandrels aligned over the gates, wherein the insulating mandrels comprise the first insulating material;

forming mandrel spacers around each insulating mandrel, wherein the mandrel spacers comprise the first insulating material;

forming a second insulating layer of the second insulating material over the transistor;

forming one or more first trenches to the sources and drains of the first gates by removing the second insulating material from portions of the transistor between the insulating mandrels; and

forming a second trench to the second gate by removing portions of the first insulating material and the second insulating material above the second gate; and

filling the first trenches and the second trench with conductive material to form first contacts to the sources and drains of the first gates and a second contact to the second gate.

24. A computer readable storage medium storing a plurality of instructions which, when executed, generate a semiconductor device that comprises:

a plurality of replacement metal gates on a semiconductor substrate, wherein first gates have sources and drains and at least one second gate is isolated from the first gates;

gate spacers of a first insulating material around each first gate;

a first insulating layer of a second insulating material between the gate spacers, wherein at least some of the second insulating material overlies sources and drains of the first gates;

one or more insulating mandrels aligned over the gates, wherein the insulating mandrels comprise the first insulating material;

mandrel spacers around each insulating mandrel, wherein the mandrel spacers comprise the first insulating material;

one or more first contacts to the sources and drains of the first gates through the first insulating layer between the mandrel spacers;

a second contact to the at least one second gate through the first insulating material above the second gate;

a third insulating layer over the transistor; and

one or more local interconnects that contact the first contacts and the second contact through the third insulating layer.