Structure and Method for MOSFETS with High-K and Metal Gate Structure

• US 20130119487A1
• Filed: 04/03/2012
• Published: 05/16/2013
• Est. Priority Date: 11/11/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Shih-Hsun, Chen, Chia-Jen, Ting, Kuo-Chiang, Lin, Jr Jung, Sun, Yun-Ju, Yamamoto, Tomonari, Kuo, Chih-Wei, Sun, Meng-Yi
• Granted Patent: US 8,912,610 B2
• Time in Patent Office: Days
• US Class Current: 257/412
• CPC Class Codes: H01L 21/0206 during, before or after processing of insulating layers
• CPC Class Codes: H01L 21/02071 the processing being a delineation, e.g. RIE, of conductive layers
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31122 of layers not containing Si, e.g. PZT, Al2O3
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate; and a gate stack disposed on the semiconductor substrate. The gate stack includes a high k dielectric material layer, a capping layer disposed on the high k dielectric material layer, and a metal layer disposed on the capping layer. The capping layer and the high k dielectric material layer have a footing structure.

Claims

1. A semiconductor structure, comprising:

a semiconductor substrate; and

a gate stack disposed on the semiconductor substrate, wherein the gate stack includes;

a high k dielectric material layer,

a capping layer disposed on the high k dielectric material layer, and

a metal layer disposed on the capping layer, wherein the capping layer and the high k dielectric material layer have a footing structure.

2. The semiconductor structure of claim 1, wherein the footing structure includes a portion of the high k dielectric material layer that horizontally extends from a bottom edge of the metal layer.

3. The semiconductor structure of claim 1, wherein the footing structure includes a portion of the capping layer that horizontally extends from a bottom edge of the metal layer.

4. The semiconductor structure of claim 1, wherein the footing structure has a horizontal dimension ranging between about 0.5 nm and about 2.5 nm along a gate length direction of the gate stack.

5. The semiconductor structure of claim 1, wherein the metal layer includes:

a work function metal film disposed on the capping layer; and

another metal film on the work function metal film.

6. The semiconductor structure of claim 1, wherein the capping layer includes titanium nitride.

7. The semiconductor structure of claim 1, further comprising an interfacial layer disposed between the semiconductor substrate and the high k dielectric material layer.

8. The semiconductor structure of claim 1, wherein the metal layer includes a reentrant sidewall profile.

9. The semiconductor structure of claim 8, wherein the sidewall of the metal layer has an angle to a top surface of the semiconductor substrate, and the angle ranges between about 85 degrees and about 90 degrees.

10. A semiconductor structure, comprising:

a semiconductor substrate; and

a gate stack disposed on the semiconductor substrate, wherein the gate stack includes;

a gate dielectric layer including a high k dielectric material layer,

a capping layer disposed on the high k dielectric material layer, and

a metal layer disposed on the capping layer, wherein the metal layer has a reentrant sidewall profile.

11. The semiconductor structure of claim 10, wherein:

the semiconductor substrate has a top surface wherein the gate stack is disposed on; and

the metal layer has a sidewall tilted to the top surface of the semiconductor substrate with an angle being less than about 90 degrees.

12. The semiconductor structure of claim 11, wherein the angle is greater than about 85 degrees.

13. The semiconductor structure of claim 10, wherein the gate dielectric layer and the capping layer includes a footing feature.

14. The semiconductor structure of claim 13, wherein the footing feature has a dimension along a gate length direction, wherein the dimension ranges between about 0.5 nm and about 2.5 nm.

15. The semiconductor structure of claim 10, wherein:

the gate dielectric layer further includes an interfacial material layer; and

the capping layer includes titanium nitride.

16. The semiconductor structure of claim 10, wherein the metal layer includes:

a work function metal film disposed on the capping layer; and

another metal film disposed on the work function metal film.

17. A method of forming a gate stack, comprising:

forming various gate material layers on a semiconductor substrate, wherein the gate material layers include a gate dielectric layer, a capping layer on the gate dielectric layer, and a polysilicon layer on the capping layer;

performing a first dry etch to pattern the polysilicon layer using a first etchant;

performing a second dry etch to control sidewall of the patterned polysilicon layer such that the sidewall of the patterned polisilicon layer is reentrant using a second etchant different from the first etchant;

performing a third dry etch to pattern the capping layer such that the capping layer includes a first footing feature; and

performing a fourth dry etch to pattern the gate dielectric layer such that the capping layer includes a second footing feature.

18. The method of claim 17, wherein:

the first etchant includes Cl₂ and CF₄; and

the second etchant includes HBr.

19. The method of claim 17, wherein the first dry etch further includes a first etch step tuned to effectively etch silicon oxide and a second etch step tuned to avoid damaging the capping layer.

20. The method of claim 17, wherein:

the third dry etch utilizes a third etchant including Cl₂ and HBr; and

the fourth dry etch utilizes a fourth etchant including Cl₂ and BCl₃.

21. The method of claim 20, wherein the fourth etch includes:

a first etch step using the fourth etchant;

thereafter, a cleaning process; and

thereafter, a second etch step using the fourth etchant to control the second footing feature.

22. The method of claim 17, further comprising replacing the polysilicon layer with a metal layer including a work function metal.